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參數資料
| 型號： | MCM32257B |
| 廠商： | Motorola, Inc. |
| 英文描述： | 256K x 32 Bit Fast Static RAM Module |
| 中文描述： | 256K × 32位高速靜態RAM模塊 |
| 文件頁數： | 4/8頁 |
| 文件大小： | 158K |
| 代理商： | MCM32257B |
MCM32257B
6–4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Output Timing Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
1.5 V
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
0 to 3.0 V
Output Load
Input Rise/Fall Time
See Figure 1A Unless Otherwise Noted
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . .
3 ns
READ CYCLE TIMING
(See Notes 1 and 2)
MCM32257B–15
MCM32257B–20
MCM32257B–25
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
tELICCH
tEHICCL
15
—
20
—
25
—
ns
3
Address Access Time
—
15
—
20
—
25
ns
Enable Access Time
—
15
—
20
—
25
ns
Output Enable Access Time
—
8
—
9
—
10
ns
Output Hold from Address Change
5
—
5
—
5
—
ns
Enable Low to Output Active
5
—
5
—
5
—
ns
4,5,6
Output Enable to Output Active
0
—
0
—
0
—
ns
4,5,6
Enable High to Output High–Z
0
6
0
7
0
8
ns
4,5,6
Output Enable High to Output High–Z
0
6
0
7
0
8
ns
4,5,6
Power Up Time
0
—
0
—
0
—
ns
Power Down Time
—
15
—
20
—
25
ns
NOTES:
1. W is high for read cycle.
2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given
device and from device to device.
5. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL). See Read Cycle 1.
AC TEST LOADS
Figure 1A
Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
5 pF
+ 5 V
OUTPUT
255
480
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