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參數資料
| 型號： | MCM62486BFN19 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | Replaced by PTH12000W : |
| 中文描述： | 32K X 9 CACHE SRAM, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 197K |
| 代理商： | MCM62486BFN19 |
MCM62486B
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC, VCCQ = 5.0 V
±
5%, TA = 0 to + 70
°
C, for device MCM62486B–11)
(VCC = 5.0 V
±
10%, VCCQ = 5.0 V or 3.3 V
±
10%, TA = 0 to + 70
°
C, for all other devices)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1A Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1, 2, and 3)
62486B–11
62486B–12
62486B–14
62486B–19
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHQV
tGLQV
tKHQX1
tKHQX2
tGLQX
tGHQZ
tKHQZ
tKHKL
tKLKH
tAVKH
tADSVKH
tDVKH
tWVKH
tADVVKH
tS0VKH
tS1VKH
15
—
20
—
20
—
25
—
ns
Clock Access Time
—
11
—
12
—
14
—
19
ns
Output Enable Access
—
5
—
5
—
6
—
7
ns
Clock High to Output Active
6
—
6
—
6
—
6
—
ns
Clock High to Q Change
3
—
3
—
4
—
4
—
ns
Output Enable to Q Active
0
—
0
—
0
—
0
—
ns
Output Disable to Q High–Z
—
6
—
6
—
6
—
7
ns
4
Clock High to Q High–Z
—
6
—
6
—
6
—
6
ns
Clock High Pulse Width
5.5
—
7
—
8
—
6
—
ns
Clock Low Pulse Width
5.5
—
7
—
8
—
6
—
ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Select
2
—
2
—
3
—
3
—
ns
5
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Select
tKHAX
tKHADSX
tKHDX
tKHWX
tKHADVX
tKHS0X
tKHS1X
2
—
2
—
2
—
2
—
ns
5
NOTES:
1. A read cycle is defined by W high or ADSP low for the setup and hold times. A write cycle is defined by W low and ADSP high for the setup
and hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care when W is sampled low.
4. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of clock (K) whenever ADSP
and ADSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges
of K when the chip is selected.Chip select must be true (S1 low and S0 high) at each rising edge of clock for the device (when ADSP or ADSC
is low) to remain enabled. Timings for S1 and S0 are similar.
AC TEST LOADS
Figure 1B
5 pF
+ 5 V
OUTPUT
255
480
Figure 1A
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
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| MCM6249 | 1M x4 Bit Static Random Access Memory |
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相關代理商/技術參數 |
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| MCM6249 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1M x4 Bit Static Random Access Memory |
| MCM6249WJ20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1M x4 Bit Static Random Access Memory |
| MCM6249WJ20R2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1M x4 Bit Static Random Access Memory |
| MCM6249WJ25 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1M x4 Bit Static Random Access Memory |
| MCM6249WJ25R2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1M x4 Bit Static Random Access Memory |
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