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參數資料
| 型號： | MCM6249WJ25 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 1M x4 Bit Static Random Access Memory |
| 中文描述： | 1M X 4 STANDARD SRAM, 25 ns, PDSO32 |
| 封裝： | 0.400 INCH, SOJ-32 |
| 文件頁數： | 5/7頁 |
| 文件大小： | 116K |
| 代理商： | MCM6249WJ25 |
MCM6249
5
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
MCM6249–20
MCM6249–25
MCM6249–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
20
—
25
—
35
—
ns
4
Address Setup Time
0
—
0
—
0
—
ns
Address Valid to End of Write
15
—
17
—
20
—
ns
Write Pulse Width
15
—
17
—
20
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
10
—
10
—
15
—
ns
Data Hold Time
0
—
0
—
0
—
ns
Write Low to Data High–Z
0
9
0
10
0
15
ns
5,6,7
Write High to Output Active
5
—
5
—
5
—
ns
5,6,7
Write Recovery Time
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con–
tention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
5. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
7. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
DATA VALID
HIGH–Z
HIGH–Z
tAVAV
tAVWH
tWHAX
tWHDX
tWHQX
tWLWH
tWLEH
tAVWL
tDVWH
tWLQZ
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
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相關代理商/技術參數 |
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| MCM6249WJ35 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1M x4 Bit Static Random Access Memory |
| MCM6249WJ35R2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1M x4 Bit Static Random Access Memory |
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