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參數資料
| 型號： | MCM6249WJ35 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | CRYSTALS 30/50 0+70 20PF 20.000MHZ ATCUT FUND HC-49/UP |
| 中文描述： | 1M X 4 STANDARD SRAM, 35 ns, PDSO32 |
| 封裝： | 0.400 INCH, SOJ-32 |
| 文件頁數： | 3/7頁 |
| 文件大?。?/td> | 116K |
| 代理商： | MCM6249WJ35 |
MCM6249
3
MOTOROLA FAST SRAM
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
All Inputs Except Clocks and DQs
E, G, W
Cin
Cck
4
5
6
8
pF
Input/Output Capacitance
DQ
CI/O
5
8
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 ns
1.5 V
. . . . . . . . . . . . . . .
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
See Figure 1a
READ CYCLE TIMING
(See Note 1)
MCM6249–20
MCM6249–25
MCM6249–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
tELICCH
tEHICCL
20
—
25
—
35
—
ns
2, 3
Address Access Time
—
20
—
25
—
35
ns
Enable Access Time
—
20
—
25
—
35
ns
4
Output Enable Access Time
—
6
—
8
—
10
ns
Output Hold from Address Change
5
—
5
—
5
—
ns
Enable Low to Output Active
5
—
5
—
5
—
ns
5, 6, 7
Output Enable Low to Output Active
0
—
0
—
0
—
ns
5, 6, 7
Enable High to Output High–Z
0
9
0
10
0
12
ns
5, 6, 7
Output Enable High to Output High–Z
0
9
0
10
0
12
ns
5, 6, 7
Power Up Time
0
—
0
—
0
—
ns
Power Down Time
—
20
—
25
—
35
ns
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con–
tention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low/E going high.
5. At any given voltage and temperature, tEHQZ max
tELQX min, and tGHQZ max
to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E
≤
VIL, G
≤
VIL).
tGLQX min, both for a given device and from device
(a)
(b)
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input re-
quirements are specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.
TIMING LIMITS
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
5 pF
+ 5 V
OUTPUT
255
480
Figure 1. AC Test Loads
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