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參數資料
| 型號： | MCM6265CP15 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 8K x 9 Bit Fast Static RAM |
| 中文描述： | 8K X 9 STANDARD SRAM, 15 ns, PDIP28 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-28 |
| 文件頁數： | 3/8頁 |
| 文件大小： | 177K |
| 代理商： | MCM6265CP15 |
MCM6265C
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
5 ns
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
See Figure 1A Unless Otherwise Noted
READ CYCLE
(See Notes 1 and 2)
– 12
– 15
– 20
– 25
– 35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
12
—
15
—
20
—
25
—
35
—
ns
3
Address Access Time
—
12
—
15
—
20
—
25
—
35
ns
Enable Access Time
—
12
—
15
—
20
—
25
—
35
ns
4
Output Enable Access Time
—
6
—
8
—
10
—
11
—
12
ns
Output Hold from Address Change
4
—
4
—
4
—
4
—
4
—
ns
Enable Low to Output Active
4
—
4
—
4
—
4
—
4
—
ns
5,6,7
Enable High to Output High–Z
0
6
0
8
0
9
0
10
0
11
ns
5,6,7
Output Enable Low to Output Active
0
—
0
—
0
—
0
—
0
—
ns
5,6,7
Output Enable High to Output High–Z
0
6
0
7
0
8
0
9
0
10
ns
5,6,7
Power Up Time
0
—
0
—
0
—
0
—
0
—
ns
Power Down Time
—
12
—
15
—
20
—
25
—
35
ns
NOTES:
1. W is high for read cycle.
2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given
device and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E1 = VIL, E2 = VIH, G = VIL).
OUTPUT
Z0 = 50
50
VL = 1.5 V
Figure 1A
Figure 1B
5 pF
+ 5 V
OUTPUT
255
480
AC TEST LOADS
The table of timing values shows either
a minimum or a maximum limit for each pa-
rameter. Input requirements are specified
from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the device point of view.
Thus, the access time is shown as a maxi-
mum since the device never provides data
later than that time.
TIMING LIMITS
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