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參數資料
| 型號： | MF10AJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Universal Monolithic Dual Switched Capacitor Filter |
| 中文描述： | DUAL SWITCHED CAPACITOR FILTER, RESISTOR PROGRAMMABLE, UNIVERSAL, CDIP20 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-20 |
| 文件頁數： | 6/20頁 |
| 文件大小： | 405K |
| 代理商： | MF10AJ |
Pin Descriptions
(Continued)
LSh(9)
Level shift pin; it accommodates various
clock levels with dual or single supply
operation. With dual
g
5V supplies, the
MF10 can be driven with CMOS clock
levels (
g
5V) and the LSh pin should be
tied to the system ground. If the same
supplies as above are used but only TTL
clock levels, derived from 0V to
a
5V
supply, are available, the LSh pin should
be tied to the system ground. For single
supply operation (0V and
a
10V) the
V
A
b
, V
D
b
pins should be connected to
the system ground, the AGND pin
should be biased at
a
5V and the LSh
pin should also be tied to the system
ground for TTL clock levels. LSh should
be biased at
a
5V for CMOS clock lev-
els in 10V single-supply applications.
CLKA(10),
CLKB(11)
Clock inputs for each switched capaci-
tor filter building block. They should both
be of the same level (TTL or CMOS).
The level shift (LSh) pin description dis-
cusses how to accommodate their lev-
els. The duty cycle of the clock should
be close to 50% especially when clock
frequencies above 200 kHz are used.
This allows the maximum time for the
internal op-amps to settle, which yields
optimum filter operation.
50/100/CL(12)
By tying this pin high a 50:1 clock-to-fil-
ter-center-frequency ratio is obtained.
Tying this pin at mid-supplies (i.e, analog
ground with dual supplies) allows the fil-
ter to operate at a 100:1 clock-to-cen-
ter-frequency ratio. When the pin is tied
low (i.e., negative supply with dual sup-
plies), a simple current limiting circuit is
triggered to limit the overall supply cur-
rent down to about 2.5 mA. The filtering
action is then aborted.
AGND(15)
This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or bi-
ased to mid-supply for single supply op-
eration. For a further discussion of mid-
supply biasing techniques see the Appli-
cations Information (Section 3.2). For
optimum filter performance a ‘‘clean’’
ground must be provided.
1.0 Definition of Terms
f
CLK
:
the frequency of the external clock signal applied to
pin 10 or 11.
f
O
:
center frequency of the second order function complex
pole pair. f
O
is measured at the bandpass outputs of the
MF10, and is the frequency of maximum bandpass gain.
(Figure 1)
f
notch
:
the frequency of minimum (ideally zero) gain at the
notch outputs.
f
z
:
the center frequency of the second order complex zero
pair, if any. If f
z
is different from f
O
and if Q
Z
is high, it can be
observed as the frequency of a notch at the allpass output.
(Figure 10)
Q:
‘‘quality factor’’ of the 2nd order filter. Q is measured at
the bandpass outputs of the MF10 and is equal to f
O
divided
by the
b
3 dB bandwidth of the 2nd order bandpass filter
(Figure 1). The value of Q determines the shape of the 2nd
order filter responses as shown in Figure 6.
Q
Z
:
the quality factor of the second order complex zero pair,
if any. Q
Z
is related to the allpass characteristic, which is
written:
H
AP
(s)
e
H
OAP
s
2
b
s
0
O
Q
Z
a
0
O2
s
2
a
s
0
O
Q
a
0
O2
where Q
Z
e
Q for an all-pass response.
H
OBP
:
the gain (in V/V) of the bandpass output at f
e
f
O
.
H
OLP
:
the gain (in V/V) of the lowpass output as f
x
0 Hz
(Figure 2).
H
OHP
:
the gain (in V/V) of the highpass output as f
x
f
CLK
/2 (Figure 3).
H
ON
:
the gain (in V/V) of the notch output as f
x
0 Hz
and as f
f
CLK
/2, when the notch filter has equal gain
above and below the center frequency(Figure 4). When the
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a (Figures 11 and 8), the two quantities
below are used in place of H
ON
.
H
ON1
:
the gain (in V/V) of the notch output as f
x
0 Hz.
H
ON2
:
the gain (in V/V) of the notch output as f
x
f
CLK
/2.
6
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