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參數(shù)資料
| 型號： | MLD2N06CL |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | VOLTAGE CLAMPED CURRENT LIMITING MOSFET |
| 中文描述： | 2 A, 58 V, 0.4 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | DPAK-3 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 194K |
| 代理商： | MLD2N06CL |
5
Motorola TMOS Power MOSFET Transistor Device Data
Figure 9. Thermal Response (MLD2N06CL)
t, TIME (s)
r
T
R
θ
JC(t) = r(t) R
θ
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) R
θ
JC(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
0.01
0.1
1.0
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
1.0E+01
D = 0.5
0.02
0.2
0.05
0.1
SINGLE PULSE
0.01
PULSE GENERATOR
Rgen
VDD
Vout
Vin
50
z = 50
50
DUT
RL
Figure 10. Switching Test Circuit
toff
OUTPUT, Vout
INVERTED
ton
tr
td(off)
tf
td(on)
90%
90%
10%
INPUT, Vin
10%
50%
90%
50%
PULSE WIDTH
Figure 11. Switching Waveforms
ACTIVE CLAMPING
SMARTDISCRETES technology can provide on–chip real-
ization of the popular gate–to–source and gate–to–drain
Zener diode clamp elements. Until recently, such features
have been implemented only with discrete components
which consume board space and add system cost. The
SMARTDISCRETES technology approach economically
melds these features and the power chip with only a slight
increase in chip area.
In practice, back–to–back diode elements are formed in a
polysilicon region monolithicly integrated with, but electrically
isolated from, the main device structure. Each back–to–back
diode element provides a temperature compensated voltage
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free
from direct interaction with the conduction regions of the
power device, thus eliminating parasitic electrical effects
while maintaining excellent thermal coupling.
To achieve high gate–to–drain clamp voltages, several
voltage elements are strung together; the MLD2N06CL uses
8 such elements. Customarily, two voltage elements are
used to provide a 14.4 volt gate–to–source voltage clamp.
For the MLD2N06CL, the integrated gate–to–source voltage
elements provide greater than 2.0 kV electrostatic voltage
protection.
The avalanche voltage of the gate–to–drain voltage clamp
is set less than that of the power MOSFET device. As soon
as the drain–to–source voltage exceeds this avalanche volt-
age, the resulting gate–to–drain Zener current builds a gate
voltage across the gate–to–source impedance, turning on
the power device which then conducts the current. Since vir-
tually all of the current is carried by the power device, the
gate–to–drain voltage clamp element may be small in size.
This technique of establishing a temperature compensated
drain–to–source sustaining voltage (Figure 7) effectively re-
moves the possibility of drain–to–source avalanche in the
power device.
The gate–to–drain voltage clamp technique is particularly
useful for snubbing loads where the inductive energy would
otherwise avalanche the power device. An improvement in
ruggedness of at least four times has been observed when
inductive energy is dissipated in the gate–to–drain clamped
conduction mode rather than in the more stressful gate–to–
source avalanche mode.
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