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參數(shù)資料
| 型號： | Q67060-S6302-A4 |
| 廠商： | SIEMENS AG |
| 英文描述： | High Speed CMOS Logic Dual 4-Stage Static Shift Registers 16-SOIC -55 to 125 |
| 中文描述： | 智能雙通道阻抗高側(cè)電源開關(guān) |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 191K |
| 代理商： | Q67060-S6302-A4 |
BTS 611 L1
Parameter and Conditions,
each channel
at T
j
= 25 °C, V
bb
= 12 V unless otherwise specified
Symbol
Values
typ
Unit
min
max
Semiconductor Group
6
Input and Status Feedback
11
)
Input resistance
T
j
=-40..150°C, see circuit page 7
Input turn-on threshold voltage
Input turn-off threshold voltage
Input threshold hysteresis
Off state input current (pin 3 or 6), V
IN
= 0.4 V,
T
j
=-40..+150°C
On state input current (pin 3 or 6), V
IN
= 3.5 V,
T
j
=-40..+150°C
Delay time for status with open load after switch
off (other channel in off state)
(see timing diagrams, page 12
), T
j
=-40..+150°C
Delay time for status with open load after switch
off (other channel in on state)
(see timing diagrams, page 12
), T
j
=-40..+150°C
Status invalid after positive input slope
(open load)
Status output (open drain)
Zener limit voltage T
j
=-40...+150°C, I
ST
= +1.6 mA:
ST low voltage
T
j
=-40...+25°C, I
ST
= +1.6 mA:
T
j
= +150°C, I
ST
= +1.6 mA:
R
I
2.5
3.5
6
k
T
j
=-40..+150°C: V
IN(T+)
T
j
=-40..+150°C: V
IN(T-)
1.7
1.5
--
--
3.5
V
V
V
--
--
V
IN(T)
I
IN(off)
--
1
0.5
--
50
μ
A
I
IN(on)
20
50
90
μ
A
t
d(ST OL4)
100
320
800
μ
s
t
d(ST OL5)
--
5
20
μ
s
T=-40 ... +150°C:
t
d(ST)
--
200
600
μ
s
V
ST(high)
V
ST(low)
5.4
--
--
6.1
--
--
--
0.4
0.6
V
11)
If a ground resistor R
GND
is used, add the voltage drop across this resistor.
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