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參數資料
| 型號： | Q67060-S6307-A7 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | High Speed CMOS Logic Quad Bilateral Switches 14-PDIP -55 to 125 |
| 中文描述： | 智能感知高端功率開關 |
| 文件頁數： | 2/15頁 |
| 文件大小： | 240K |
| 代理商： | Q67060-S6307-A7 |
BTS 640 S2
Semiconductor Group
Page 2
2003-Oct-01
Pin
1
2
3
4
5
Symbol
ST
GND
IN
Vbb
IS
Function
Diagnostic feedback: open drain, invers to input level
Logic ground
Input, activates the power switch in case of logical high signal
Positive power supply voltage, the tab is shorted to this pin
Sense current output, proportional to the load current, zero in
the case of current limitation of load current
Output, protected high-side power output to the load.
Both output pins have to be connected in parallel for operation
according this spec (e.g. k
ILIS
).
Design the wiring for the max. short circuit current
6 & 7
OUT
(Load, L)
Maximum Ratings
at
T
j
= 25 °C unless otherwise specified
Parameter
Supply voltage
(overvoltage protection see page 4)
Supply voltage for full short circuit protection
T
j Start=-40 ...+150°C
Load dump protection
1
)
VLoadDump = VA + Vs, VA = 13.5V
R
I2)= 2
,
R
L= 1
,
t
d= 200 ms, IN= low or high
Load current
(Short circuit current, see page 5)
Operating temperature range
Storage temperature range
Power dissipation
(DC), TC
≤
25 °C
Inductive load switch-off energy dissipation, single pulse
Vbb = 12V,
T
j,start = 150°C,
T
C = 150°C const.
I
L
=
12.6
A, Z
L
=
4,2
mH, 0
:
I
L
=
4
A, Z
L
=
330
mH, 0
:
Electrostatic discharge capability (ESD)
(Human Body Model)
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5k
; C=100pF
Input voltage
(DC)
Current through input pin
(DC)
Current through status pin
(DC)
Current through current sense pin
(DC)
see internal circuit diagrams page 8
Symbol
V
bb
V
bb
Values
Unit
43
34
V
V
V
Load dump3
)
60
V
I
L
T
j
T
stg
P
tot
E
AS
E
AS
V
ESD
self-limited
-40 ...+150
-55 ...+150
A
°C
85
W
0,41
3,5
1.0
4.0
8.0
J
IN:
ST, IS:
kV
V
IN
I
IN
I
ST
I
IS
-10 ... +16
V
±
2.0
±
5.0
±
14
mA
1
) Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins (a 150
resistor in the GND connection is recommended).
2)
R
I
= internal resistance of the load dump test pulse generator
3)
V
Load dump
is setup without the DUT connected to the generator according to ISO 7637-1 and DIN 40839
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