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參數資料
| 型號： | DS2740U+T&R |
| 廠商： | Maxim Integrated |
| 文件頁數： | 7/16頁 |
| 文件大小： | 304K |
| 描述： | IC CURRENT GAUGE(15BIT) 8UMAX |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 功能： | 電流計（15 位） |
| 輸入電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS2740
7 of 16
ACR RANGE
R
SNS
PART
V
IS1
- V
IS2
20m?
15m?
10m?
5m?
DS2740U
DS2740BU
?04.8mVh ?0.24Ah ?3.65Ah ?0.48Ah ?0.96Ah
MEMORY
The DS2740 has memory space with registers for instrumentation, status, and control. When the MSB of
a two-byte register is read, both the MSB and LSB are latched and held for the duration of the Read Data
command to prevent updates during the read and ensure synchronization between the two register bytes.
For consistent results, always read the MSB and the LSB of a two-byte register during the same Read
Data command sequence.
Table 3. MEMORY MAP
ADDRESS (HEX)
DESCRIPTION
READ/WRITE
00
Reserved
01
Status Register
R/W
02 to 07
Reserved
08
Special Feature Register
R/W
09 to 0D
Reserved
0E
Current Register MSB
R
0F
Current Register LSB
R
10
Accumulated Current Register MSB
R/W
11
Accumulated Current Register LSB
R/W
12 to FF
Reserved
STATUS REGISTER
The format of the status register is shown in Figure 5. The function of each bit is described in detail in the
following paragraphs.
Figure 5. STATUS REGISTER FORMAT
ADDRESS 01h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
X SMOD
X RNAOP
X
X
X
X
SMODSLEEP Mode Enable. A value of 1 allows the DS2740 to enter Sleep mode when DQ is low for
2s. A value of 0 disables DQ related transitions to Sleep mode. The power-up default of SMOD = 0.
RNAOPRead Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address
command to 33h, while a 1 sets the opcode to 39h. The power-up default of RNAOP = 0.
XReserved bits.
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