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參數資料
| 型號： | DS7505U+T&R |
| 廠商： | Maxim Integrated |
| 文件頁數： | 3/14頁 |
| 文件大小： | 197K |
| 描述： | IC DGTL THERMOMETER 2WIRE 8-USOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 功能： | 溫度計，恒溫計 |
| 傳感器類型： | 內部 |
| 感應溫度： | -55°C ~ 125°C |
| 精確度： | ±2°C（最小值） |
| 拓撲： | ADC（三角積分型），比較器，寄存器庫 |
| 輸出類型： | I²C?/SMBus? |
| 輸出警報： | 無 |
| 輸出風扇： | 無 |
| 電源電壓： | 1.7 V ~ 3.7 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
Digital Thermometer and Thermostat
_______________________________________________________________________________________ 3
Note 1: All voltages are referenced to ground.
Note 2: Internal heating caused by O.S. loading causes the DS7505 to read approximately 0.5?/SPAN>C higher if O.S. is sinking the
max-rated current.
Note 3: Specified in 12-bit conversion mode. Quantization error must be considered when converting in lower resolutions.
Note 4: I
DD
specified with O.S. pin open.
Note 5: I
DD
specified with V
DD
at 3.0V and SDA, SCL = 3.0V, T
A
= -55癈 to +85癈.
Note 6: I
DD
specified with A0, A1, A2 = 0V or V
DD
.
Note 7: V
DD
must be > 2.0V.
Note 8: E
2
Copy occurs at +25癈.
Note 9: See the timing diagram (Figure 1). All timing is referenced to 0.9 x V
DD
and 0.1 x V
DD
.
Note 10: After this period, the first clock pulse is generated.
Note 11: The DS7505 provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCLs
falling edge.
Note 12: For example, if C
B
= 300pF, then t
R(MIN)
= t
F(MIN)
= 50ns.
Note 13: This timeout applies only when the DS7505 is holding SDA low. Other devices can hold SDA low indefinitely and the
DS7505 does not reset.
AC ELECTRICAL CHARACTERISTICS (continued)
(1.7V d V
DD
d 3.7V, T
A
= -55癈 to +125癈, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Data Retention
t
EEDR
-40癈 to +125癈 (Note 8)
10
Years
Bus Free Time Between a STOP
and START Condition
t
BUF
(Note 9)
1.3
約
START and Repeated START
Hold Time from Falling SCL
t
HD:STA
(Notes 9, 10)
600
ns
Low Period of SCL
t
LOW
(Note 9)
1.3
約
High Period of SCL
t
HIGH
(Note 9)
0.6
約
Repeated START Condition
Setup Time to Rising SCL
t
SU:STA
(Note 9)
600
ns
Data-Out Hold Time from Falling
SCL
t
HD:DAT
(Notes 9, 11)
0
0.9
約
Data-In Setup Time to Rising
t
SU:DAT
(Note 9)
100
ns
Rise Time of SDA and SCL
(Receive)
t
R
(Notes 9, 12)
20 +
0.1C
B
300
ns
Fall Time of SDA and SCL
(Receive)
t
F
(Notes 9, 12)
20 +
0.1C
B
300
ns
Spike Suppression Filter Time
(Deglitch Filter)
t
SS
0
50
ns
STOP Setup Time to Rising SCL
t
SU:STO
(Note 9)
600
ns
Capacitive Load for Each Bus
Line
C
B
400
pF
Input Capacitance
C
I
5
pF
Serial Interface Reset Time
t
TIMEOUT
SDA time low (Note 13)
75
325
ms
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