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參數資料
| 型號： | L9310 |
| 英文描述： | Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device |
| 中文描述： | 線路接口和線路接入電路全功能用戶接口，振鈴繼電器，測試接入設備 |
| 文件頁數： | 12/60頁 |
| 文件大小： | 1053K |
| 代理商： | L9310 |
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Data Sheet
July 2001
Full-Feature SLIC, Ringing Relay, and Test Access Device
L9310 Line Interface and Line Access Circuit
12
Agere Systems Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
17
Symbol
TESTLEV
Type
O
Name/Function
Test Level Output.
This output pin will provide a voltage that is proportional to either
the dc line voltage, dc line current, ac line voltage, ac line current, or internal refer-
ence voltage, dependent upon which operational state is selected.
PPM Out.
Connect a resistor from this node to ITR for hybrid cancellation of meter
pulse signal.
Ring Trip Sense.
Sense input for the ring trip detector.
Ring Lead Ringing Access Switch.
Ringing relay connects this pin to pin RRING.
Connect this pin to pin PR through a 400
current-limiting resistor.
Ringing Access.
Input to solid-state ringing access switch. Connect to ringing gen-
erator.
Protected Ring.
The output of the ring driver amplifier and input to loop sensing
connected through solid-state break switch. Connect to subscriber loop through
overvoltage/current protection.
Protected Tip.
The output of the tip driver amplifier and input to loop sensing con-
nected through solid-state break switch. Connect to subscriber loop through over-
voltage/current protection.
Tip Ringing Return.
Ring relay connects this pin to PT. Connect to ringing supply
return.
Loop Status.
The output of the loop status detector (loop start detector wired-OR
with ring trip detector). This loop status supervision output is not controlled by the
data latch.
Data Control Input.
See Table 2, Primary Control States and Table 3, Secondary
Control States for details.
Data Control Input.
See Table 2, Primary Control States and Table 3, Secondary
Control States for details.
Data Control Input.
See Table 2, Primary Control States and Table 3, Secondary
Control States for details.
Data Control Input.
See Table 2, Primary Control States and Table 3, Secondary
Control States for details.
Reset.
A logic low will override the B[0:3] and LATCH inputs and reset the state of
the SLIC to the disconnect state and the switch to the all-off state.
Latch Control Input.
Edge-level sensitive control for data latches.
5 V Digital Power Supply.
5 V supply for digital circuitry.
Digital Ground.
Ground return for V
DD
current.
Tip/Ring Ground Detect.
When high, this open collector output indicates the pres-
ence of a ring ground or a tip ground. This supervision output may be used in ground
start, ground key, or common-mode fault detection applications. It has an internal
pull-up.
Common-Mode Current Sense.
To program tip or ring ground sense threshold,
connect a resistor to ground and connect a capacitor to AGND to filter 50 Hz/60 Hz.
If unused, the pin is connected to ground.
Tip/Ring Voltage Output.
This output is a voltage that is directly proportional to the
differential tip/ring current. A resistor from this node to ITR sets the device
transim-
pedance. Gain shaping for termination impedance with a COMBO I codec is also
achieved with a network from this node to ITR.
18
PPMOUT
O
19
20
RTS
RSW
I
O
21
RRING
I
22
PR
I/O
23
PT
I/O
24
TRING
O
25
NSTAT
O
26
B3
I
27
B2
I
28
B1
I
29
B0
I
30
RESET
I
31
32
33
34
LATCH
V
DD
DGND
TRGDET
I
P
G
O
35
ICM
I
36
VTX
O
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