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| 型號(hào)： | MC68B912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 105/128頁(yè) |
| 文件大小： | 748K |
| 代理商： | MC68B912B32FU8 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
105
The BDLC port DLC functions as a general-purpose I/O port. BDLC functions takes precedence over
the general-purpose port when enabled. Read or write anytime.
BDLCEN — BDLC Enable
0 = Configure BDLC I/O pins as general-purpose I/O pins. BDLC is off.
1 = Configure I/O pins for BDLC function. BDLC is active.
PUPDLC — BDLC Pull-Up Enable
0 = Disconnects internal pull-ups from PORTDLC I/O pins.
1 = Connects internal pull-ups to PORTDLC I/O pins.
RDPDLC — BDLC Reduced Drive
0 = Configure PORTDLC I/O pins for normal drive strength.
1 = Configure PORTDLC I/O pins for reduced drive strength.
Holds data to be driven out on port DLC pins or data received from port DLC pins.
PORTDLC can be read anytime. When configured as an input, a read will return the pin level. When
configured as output, a read will return the latched output data. Writes will not change pin state when
the pins are configured for BDLC output. Upon reset pins are configured for general-purpose high im-
pedance inputs.
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
14
15
16
17
18
19
20
21
22
23
24
DLCSCR
— Port DLC Control Register
$00FD
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
BDLCEN
PUPDLC
RDPDLC
RESET:
0
0
0
0
0
0
0
0
PORTDLC
— Port DLC Data Register
$00FE
Bit 7
6
5
4
3
2
1
Bit 0
0
Bit 6
5
4
3
2
1
Bit 0
RESET:
0
–
–
–
–
–
–
–
Alt. Pin
Function
–
–
–
–
–
–
DLCTX
DLCRX
Table 36 Offset Bit Values and Transceiver Delay
BARD Offset Bits
(BO3, BO2, BO1, BO0)
Expected Delay (
μ
s
)
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