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參數資料
| 型號： | MC68CK338 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數： | 113/133頁 |
| 文件大小： | 798K |
| 代理商： | MC68CK338 |
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MC68CK338
MC68CK338TS/D
MOTOROLA
113
NOTES:
1. Tested with a 32.768 kHz reference.
2. All internal registers retain data at 0 Hz.
3. Assumes that stable V
DDSYN
is applied, and that the crystal oscillator is stable. Lock time is measured from
the time V
DD
and V
DDSYN
are valid until RESET is released. This specification also applies to the period re-
quired for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYN-
CR) while the PLL is running, and to the period required for the clock to lock after LPSTOP.
4. This parameter is periodically sampled rather than 100% tested.
5. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
external resistance from the XFC pin due to external leakage must be greater than 15 M
to guarantee this
specification. Filter network geometry can vary depending upon operating environment.
6. Proper layout procedures must be followed to achieve specifications.
7. Internal VCO frequency (f
VCO
) is determined by SYNCR W and Y bit values.
The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f
sys
= f
VCO
÷
4.
When X = 1, the divider is disabled, and f
sys
= f
VCO
÷
2.
X must equal one when operating at maximum specified f
sys
.
8. Jitter is the average deviation from the programmed frequency measured over the specified interval at max-
imum f
sys
. Measurements are made with the device powered by filtered supplies and clocked by a stable ex-
ternal clock signal. Noise injected into the PLL circuitry via V
DDSYN
and V
SS
and variation in crystal oscillator
frequency increase the J
clk
percentage for a given interval. When clock jitter is a critical constraint on control
system operation, this parameter should be measured during functional testing of the final system.
Table 69 Clock Control Timing
(V
DD
and V
DDSYN
= 2.7 to 3.6 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
Num
Characteristic
Symbol
Min
Max
Unit
1
PLL Reference Frequency Range
1
System Frequency
2
On-Chip PLL System Frequency Range
External Clock Operation
f
ref
25
50
kHz
2
f
sys
dc
4(f
ref
)
dc
14.4
14.4
14.4
MHz
3
PLL Lock Time
1,
3, 4, 5, 6
VCO Frequency
7
Limp Mode Clock Frequency
SYNCR X bit = 0
SYNCR X bit = 1
t
lpll
f
VCO
—
20
ms
4
—
2 (f
sys
max)
MHz
5
f
limp
—
—
f
sys
max/2
sys
max
MHz
6
CLKOUT Jitter
1,
4, 5, 6, 8
Short term (5
μ
s interval)
Long term (500
μ
s interval)
J
clk
– 0.5
– 0.05
0.5
0.05
%
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