- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371046 > MC68CK338 (Motorola, Inc.) Highly Integrated, Low-Power, 32-Bit Microcontroller PDF資料下載
參數(shù)資料
| 型號： | MC68CK338 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 60/133頁 |
| 文件大?。?/td> | 798K |
| 代理商： | MC68CK338 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當(dāng)前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁
MOTOROLA
60
MC68CK338
MC68CK338TS/D
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
STOP places the QSM in a low-power state by disabling the system clock in most parts of the module.
The QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is
not readable. However, writes to RAM or any register are guaranteed to be valid while STOP is assert-
ed. STOP can be negated by the CPU and by reset.
The system software must stop each submodule before asserting STOP to avoid complications at re-
start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and
the operation should be verified for completion before asserting STOP. The QSPI submodule should be
stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.
FRZ1 — Freeze 1
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.
FREEZE is asserted whenever the CPU enters the background mode.
FRZ0 — Freeze 0
Reserved
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted
0 = User access
1 = Supervisor access
SUPV defines the assignable QSM registers as either supervisor-only data space or unrestricted data
space.
IARB — Interrupt Arbitration Identification Number
The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
module that can generate interrupt requests must be assigned a unique, non-zero IARB field value.
Refer to
3.9 Interrupts
for more information.
QTEST —
QSM Test Register
QTEST is used during factory testing of the QSM. Accesses to QTEST must be made while the MCU
is in test mode.
$YFFC02
QILR determines the priority level of interrupts requested by the QSM and the vector used when an in-
terrupt is acknowledged.
ILQSPI — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
QILR —
QSM Interrupt Levels Register
$YFFC04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
ILQSPI
ILSCI
QIVR
RESET:
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68EC060 | 32-Bit Microprocessors.(32位微處理器) |
| MC68EN360RC25V | QUad Integrated Communications Controller Users Manual |
| MC68EN360CFE25 | QUad Integrated Communications Controller Users Manual |
| MC68EN360FE25 | AC 4C 4#12 PIN PLUG 023 |
| MC68EN360FE25V | QUad Integrated Communications Controller Users Manual |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68CK338CPV14 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68CK338CPV14B1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68CM16Z1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CM16Z1CFC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CM16Z1CPV16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。