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| 型號(hào)： | MC68HC11E9VFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:5.1"; External Width:3"; External Depth:5.1" |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 121/268頁(yè) |
| 文件大小： | 3696K |
| 代理商： | MC68HC11E9VFU2 |
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Serial Communications Interface (SCI)
SCI Error Detection
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
121
7.5.2 Address-Mark Wakeup
The serial characters in this type of wakeup consist of seven (eight if M = 1)
information bits and an MSB, which indicates an address character (when set to 1,
or mark). The first character of each message is an addressing character (MSB =
1). All receivers in the system evaluate this character to determine if the remainder
of the message is directed toward this particular receiver. As soon as a receiver
determines that a message is not intended for it, the receiver activates the RWU
function by using a software write to set the RWU bit. Because setting RWU inhibits
receiver-related flags, there is no further software overhead for the rest of this
message.
When the next message begins, its first character has its MSB set, which
automatically clears the RWU bit and enables normal character reception. The first
character whose MSB is set is also the first character to be received after wakeup
because RWU gets cleared before the stop bit for that frame is serially received.
This type of wakeup allows messages to include gaps of idle time, unlike the
idle-line method, but there is a loss of efficiency because of the extra bit time for
each character (address bit) required for all characters.
7.6 SCI Error Detection
Three error conditions – SCDR overrun, received bit noise, and framing – can
occur during generation of SCI system interrupts. Three bits (OR, NF, and FE) in
the serial communications status register (SCSR) indicate if one of these error
conditions exists.
The overrun error (OR) bit is set when the next byte is ready to be transferred from
the receive shift register to the SCDR and the SCDR is already full (RDRF bit is
set). When an overrun error occurs, the data that caused the overrun is lost and
the data that was already in SCDR is not disturbed. The OR is cleared when the
SCSR is read (with OR set), followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including
the start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit
is cleared when the SCSR is read (with FE equal to 1) followed by a read of the
SCDR.
When no stop bit is detected in the received data character, the framing error (FE)
bit is set. FE is set at the same time as the RDRF. If the byte received causes both
framing and overrun errors, the processor only recognizes the overrun error. The
framing error flag inhibits further transfer of data into the SCDR until it is cleared.
The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read
of the SCDR.
F
Freescale Semiconductor, Inc.
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PDF描述 |
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| MC68HC11E20VFU2 | MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:5.1"; External Width:5.1"; External Depth:3" |
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