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參數(shù)資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 220K |
| 代理商： | MC68HC705V8 |
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AN1224/D
MOTOROLA
15
If the Type bit of the first byte is clear, indicating that the message is a functionally addressed message, the
second byte of the message, the target address byte, is then retrieved. This byte is compared to each
functional I.D. for which a Received Message Buffer has been reserved. If a match is found, the Received
Message Buffer Pointer corresponding to that functional I.D. is loaded into MCU RAM location "buff_ndx".
The data bytes are then retrieved and stored in the MCU RAM message buffer which corresponds to that
functional I.D. The target and source address bytes of the message are not retained. It is not necessary to
retain these bytes of the message, since a logical assumption is that the functional I.D. must be known to
the receiver already, and the source address is of no use since the function, and not the source, of the
message data is what is important.
When a message of interest to the user is received, the RXMS interrupt will be cleared when the number of
received message bytes in the MRSR is read prior to retrieval of the message data bytes. Once the data
bytes of interest are retrieved, then the MRSR is written to, releasing the Rx buffer back to the MDLC. If a
message which does not pass the message filtering criteria is received, the write to the MRSR to release
the Rx buffer and discard the message also serves to clear the RXMS interrupt generated by that
message.
This procedure results in each MCU RAM receive buffer containing the latest data received for each
specific functional I.D., and for the most recently received node-to-node message. The CPU can access
this data whenever it needs updated information. Whenever this stored data is accessed, however, the
user should first set the I-bit to inhibit interrupts. If a receive interrupt is serviced while the CPU is
accessing this stored data, it is possible that the CPU could end up reading partial data from two different
received messages.
Refer to
Figure 7a MDLC Interrupt Service Routine (cont.’d)
and
Figure 7b MDLC Interrupt Service
Routine (concluded)
for a flow diagram of the sequence followed when an MDLC interrupt of the CPU
occurs.
Error Handling
The basic driver routines in Appendix A do not contain extensive error handling procedures. Since any
message in which an error is detected is discarded by the receiver, the user has no need (or way) to
monitor receive errors as they occur. The user can monitor, to a limited extent, the status of the multiplex
bus through the use of a test message, or by monitoring time between received messages.
When transmitting a message, the user can determine whether a loss of arbitration or a transmission error
has occurred by checking messages received after a transmission has been originated. If messages of
higher priority are continually received, the user may wish to abort the transmission and retry using a
higher message priority. If more than one message of lower priority is detected following the initiation of a
message transmission, the user may assume a transmit error occurred, and initiate another attempt to
transmit the message, if so desired.
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