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參數資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數： | 7/28頁 |
| 文件大小： | 220K |
| 代理商： | MC68HC705V8 |
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AN1224/D
MOTOROLA
7
on a J1850-compatible serial multiplex bus. When a message is ready for transmission onto the multiplex bus,
the CPU simply stores the entire message into the MDLC transmit buffer, loads the number of bytes to be
transmitted into the MDLC transmit control register (MTCR), and then returns to normal application
processing. The MDLC performs all of the necessary bus acquisition, frame transmission, arbitration and
error detection to ensure that only complete, error-free frames are transmitted. When frames are received
from the multiplex bus, the MDLC module performs the necessary bit and symbol decoding and frame
verification, interrupting the CPU only when complete messages have been received from the multiplex bus
error-free. Also, because all of the major components necessary for multiplex bus communication are
integrated onto the MDLC module, including the analog transceiver, only a few inexpensive external discrete
components are required to interface the MDLC module to the multiplex bus physical layer.
Figure 3. MC68HC705V8 Power Supply and Multiplex Bus Interface Circuit
Control and Status Registers
The MDLC contains two registers which allow the user to configure the module and control message
transmission, and two registers for relaying status information about the module and about received
messages to the CPU. The MDLC Control Register (MCR) contains control bits which are used to set the
receive mode of the MDLC module, to select the rate of transmission onto the multiplex bus, to enable MDLC
1 M
4.19 MHz
27
ρ
F
OSC1
OSC2
6
5
M
C
6
8
H
C
7
0
5
V
8
27
ρ
F
BUS
LOAD
REXT1
REXT2
V
BATT
V
SSA
2
V
DD
V
SSD
V
SSD
V
DD
V
SSA
1
V
CCA
NOTE: Ferrite Bead F1 used for suppression of EMI above 5 MHz on the bus line; characteristics of ferrite bead should
be similar to TDK# HF70ACB453215.
V
IGN
470
ρ
F
J1850
Multiplex
Bus
10.6 k
F1
24
23
31.6 k
1%
24.9 k
1%
27
28
0.001
μ
F 0.1
μ
F
10
μ
F
tant.
+12 V
1N5822
P6KE30A
0 V
P6KE15A
22
25
— Denotes Chassis Ground
— Denotes Circuit Ground
V
DD
C1
R1
29
V
IGN
0.1
μ
F
41
0.1
μ
F
0.1
μ
F
40
30
31
3
4
+5-V supply
+5-V V
CCA
supply
provided from
V
DD
supply pin
PIN
NUMBERS
CORRESPOND
TO
68-
PIN
PACKAGE
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