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參數(shù)資料
| 型號： | MC92053 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 45K |
| 代理商： | MC92053 |
MOTOROLA, INC. 1997
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this Data Sheet by MC92053/D
Product Brief
MC92053
Quad FTTC Network Framer
The MC92053 is a peripheral device composed of four parallel bidirectional TC-sublayer functional units with
UTOPIA Level 2 compliant ATM-layer ports.
MC92053 Features
Implements the DAVIC short-range baseband asymmetrical physical layer standard
Interfaces to an ATM-layer device using a multi-PHY UTOPIA Level 2 compliant interface
Provides an 8-bit system interface as a generic slave device
IEEE 1149.1 (JTAG) boundary scan test port
3.3 V operation with TTL compatibility on I/O pins
Extended temperature operation: -40 to 85
°
C
Available in 208 Pin Plastic Quad Flat Package
Each of the four framers:
Provides a bit rate of up to 51.84 Mbit/sec downstream
Controls the TIme Division Multiple Access (TDMA) among up to 4 user devices
Supports a bit rate of up to 6.48 Mbit/s upstream, including DAVIC Bit Rates B, C, and D
Includes serial data link interfaces for upstream and downstream frames
Performs convolutional interleaving of the downstream payload blocks for the full range of interleaving
depths (M = 1-31) using an external 32K x 16 SRAM shared by all four framers
Performs Reed-Solomon encoding of the downstream frames and decoding of the upstream frames
Performs ATM cell TC functions, including HEC-based error detection and correction on the upstream data
Includes serial data interfaces to Physical Media Devices (PMD).
Figure 1. MC92053 Block Diagram
Microprocessor
Interface
JTAG Controller
Tx
UTOPIA
I/F
Rx
UTOPIA
I/F
Framer #1
Framer #2
Framer #3
Framer #0
MC92053
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
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