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參數資料
| 型號： | MC92053 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 3/6頁 |
| 文件大小： | 45K |
| 代理商： | MC92053 |
MC92053
Motorola
3
Frame Header Generation Block
The frame header generation block generates the 12
header bytes (excluding the two sync bytes) for each
downstream frame. One of the main functions of this
block is to allocate grants to the user devices. A pro-
grammable grant allocation mechanism is implemented
to provide a combination of fixed and on-demand allo-
cations in order to support both CBR and ABR connec-
tions.
Randomizers
The data is randomized for better transmission perfor-
mance. The two randomizers are identical. One is used
for 12 header bytes per frame, and the other is used for
the (12 * 58) payload bytes per frame.
Reed-Solomon Encoders
There are two Reed-Solomon encoders. One encoder
adds four parity bytes to the 12 header bytes to produce
a (16,12) RS code. The other encoder adds eight parity
bytes to each block of 58 payload bytes to produce
(66,58) RS codes.
Interleaver
The interleaver block spreads the blocks of payload
data over a large period of time. Transmitting inter-
leaved data allows for better correction of bursts of er-
rors because the deinterleaver at the receiving end
spreads the incorrect data over many blocks so that the
Reed-Solomon decoder can correct the small number
of errors in each block.
The interleaver separates the data byte stream into 33
branches. Each of the branches is delayed by a differ-
ent amount, and then they are recombined into a single
data stream. The delay of branch k (0
≤
k
≤
32) is M * k.
M is the programmable Interleaving Depth Parameter
which is included in the downstream frame header and
ranges from 0 to 31. M=0 effectively disables the inter-
leaver.
The delay of the interleaver/deinterleaver combination
is 1056 * M payload byte periods.
The four interleavers are implemented together since
the downstream frame alignment is synchronized
among the four framers. This requires the same value
of M to be used for all four framers.
An external SRAM must be provided for temporary stor-
age of the data unless interleaving is disabled.
Tx PMD Interface
The Tx PMD interface block constructs the downstream
frames by combining the 2 sync bytes with 1 header
block and 12 payload blocks. It transmits a serial data
stream along with a signal that indicates the symbol
alignment.
Rx PMD Interface
The receive PMD interface consists of a clock signal, a
data signal, and a start-of-frame signal. The clock signal
is only required to be active while valid data is being
transferred. The start-of-frame signal indicates the first
bit of each frame.
Reed-Solomon Decoder
The Reed-Solomon decoder operates on the 65-byte
RS codeword of the upstream frame. It either corrects
up to 4 bytes of the 57 data bytes or declares the frame
to be uncorrectable, in which case the frame is discard-
ed.
Derandomizer
The received data has been randomized on the user
side for better transmission performance. The deran-
domizer performs the inverse function to restore the
original data. The derandomizer is initialized at the be-
ginning of each frame.
Frame Header Interpretation Block
The frame header interpretation block extracts the use-
ful information from the received frame header. It pro-
vides status information to both the frame header
generation block and to the processor.
Data Link Extraction Block
The data link extraction block optionally provides the
data link bytes of the upstream frame headers to a serial
data link controller (e.g., MC68360 QUICC) for further
processing. The received upstream data link bytes are
filtered on the basis of the device ID in the data link ad-
dress byte according to a programmable filter. The fil-
tered data link stream is extracted using a clock pin and
a data pin.
Rx Cell Functions
The receive cell functions block checks the received
HEC value against the calculated value and corrects
single-bit errors in the header. Any cell with non-correct-
able errors is discarded. Also, all idle cells are discard-
ed.
The cell functions block transfers entire ATM cells to the
receive cell FIFO. A count of the cells transferred to the
receive cell FIFO is maintained.
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