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| 型號： | MC92600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口) |
| 中文描述： | 高速，全雙工，串行數(shù)據(jù)接口（高速全雙工串行數(shù)據(jù)接口） |
| 文件頁數(shù)： | 11/82頁 |
| 文件大小： | 1056K |
| 代理商： | MC92600 |
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Chapter 1. Introduction
1-1
Chapter 1
Introduction
The purpose of this users manual is to explain the functionality of the WarpLinka Quad
interface and enable its use by software and hardware developers. The audience for this
publication, therefore, consists of developers and application programmers who are
building datapath switches and applications.
1.1 WarpLink Quad Overview
The MC92600 WarpLink Quad is a high-speed, full-duplex, serial data interface that can
be used to transmit or receive data between chips across a board, through a backplane, or
through cabling. WarpLinks four transceivers each transmit or receive coded data at a rate
of 1.0 gigabit per second (Gbps) through each of the four 1.25 gigabaud links. WarpLink
Quads rich feature set makes it easily adaptable to many applications.
WarpLink Quad is carefully designed for low-power consumption. Its 0.25 micron CMOS
implementation nominally consumes 780mW with all links operating at full speed.
The WarpLink Quad device is based upon the WarpLink family of embedded transceivers.
SpeciTcally, WarpLink generation 1.5 is used as the basic transceiver around which the chip
is constructed.
1.2 Features
The following are the features of the WarpLink Quad:
￥
Four full-duplex differential data links.
￥
Each transceiver can operate at 1Gbps (1.25 Gbaud) or 500Mbps (625 Mbaud), all
transceivers run at an 8Gbps full duplex data rate.
￥
Low power, approximately 780mW under typical conditions, while operating all
transceivers at full speed.
￥
Internal 8B10B encoder/decoder is accessed through the byte interface or is
bypassed in 10-bit interface mode.
￥
Single and double data rate interfaces.
￥
Received data may be aligned to the recovered clock or to the reference clock.
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