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參數資料
| 型號： | 4432-T-B1 B 915 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 34/47頁 |
| 文件大小： | 799K |
| 描述： | KIT DEV TEST EZRADIOPRO SI4432 |
| 標準包裝： | 1 |
| 附件類型： | 測試卡，收發器，915MHz |
| 適用于相關產品： | EZRadioPRO? |
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Si4430/31/32-B1
34
Rev 1.1
4.2.2. Direct Mode
For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be desirable to
use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely.
In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real time" (i.e.,
not stored in a register for transmission at a later time). A variety of pins may be configured for use as the TX Data
input function.
Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is desired (only
the TX Data input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0]
field, and various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field.
The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing
purposes.
In RX direct mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO pins. The
microcontroller may then process the RX data without using the FIFO or packet handler functions of the RFIC. In
RX direct mode, the chip must still acquire bit timing during the Preamble, and thus the preamble detection
threshold (SPI Register 35h) must still be programmed. Once the preamble is detected, certain bit timing functions
within the RX Modem change their operation for optimized performance over the remainder of the packet. It is not
required that a Sync word be present in the packet in RX Direct mode; however, if the Sync word is absent then the
skipsyn bit in SPI Register 33h must be set, or else the bit timing and tracking function within the RX Modem will
not be configured for optimum performance.
4.2.2.1. Direct Synchronous Mode
In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In direct
synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external device that is
providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal to the programmed
data rate. The external modulation source (e.g., MCU) must accept this TX Clock signal as an input and respond
by providing one bit of TX Data back to the RFIC, synchronous with one edge of the TX Clock signal. In this
fashion, the rate of the TX Data input stream from the external source is controlled by the programmed data rate of
the RFIC; no TX Data bits are made available at the input of the RFIC until requested by another cycle of the TX
Clock signal. The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored
internally for later transmission).
All modulation types (FSK/GFSK/OOK) are valid in TX direct synchronous mode. As will be discussed in the next
section, there are limits on modulation types in TX direct asynchronous mode.
4.2.2.2. Direct Asynchronous Mode
In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream. Instead,
the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data applied to its TX
Data input pin, at whatever rate it is supplied. This means that there is no longer a need for a TX Clock output
signal from the RFIC, as there is no synchronous "handshaking" between the RFIC and the external data source.
The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for
later transmission).
It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode. The chip
still internally samples the incoming TX Data stream to determine when edge transitions occur; however, rather
than sampling the data at a pre-programmed data rate, the chip now internally samples the incoming TX Data
stream at its maximum possible oversampling rate. This allows the chip to accurately determine the timing of the bit
edge transitions without prior knowledge of the data rate. (Of course, it is still necessary to program the desired
peak frequency deviation.)
trclk[1:0]
TX/RX Data Clock Configuration
00
No TX Clock (only for FSK)
01
TX/RX Data Clock is available via GPIO (GPIO needs programming accordingly as well)
10
TX/RX Data Clock is available via SDO pin (only when nSEL is high)
11
TX/RX Data Clock is available via the nIRQ pin
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