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參數資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數： | 10/27頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
ended inputs. The receiver consists of a differential input Schmitt Trigger comparator with 50mV of
hysteresis to prevent noise from corrupting the recovered data. The minimum input signal is 200 mV. If
the digital mode is selected only single ended operation is supported; the input signal must comply with
the input voltage specifications in DC ELECTRICAL CHARACTERISTICS. In order to select this interface
the AC97_MODE pin must be tied to GND and the I2S_SPDIF_Sel must be 1.
6.3
Input from AC’97
To select this interface the AC97_MODE pin must be tied to VDD (I2S_SPDIF_Sel is don’t care). The
AC’97 interface can be configured either as the primary or secondary device using the external
configuration pin SA. This interface supports four discrete sampling frequencies, according to the
Variable and Double Rate Audio Codec ’97 specification. Table 6 summarizes the slot usage for each
one of these frequencies and Table 7 summarizes the different input configurations
Table 6
Freq.
Slot 3
Slot4
Slot 6
Slot 7
Slot 8
Slot 9
Slot 10
Slot 11
Slot 12
48
44.1
88.2*
Left
Left
Left
Right
Right
Right
Center
Center
Surr.L
Surr.L
Surr.R
Surr.R
LFE
Left (n+1)
Right (n +1)
Center
(n+1)
Center
(n+1)
96
Left
Right
Center
Left (n+1)
Right (n+1)
*Slots 3, 4 and 6 are always requested. Slots 10, 11, and 12 are requested only when needed
Table 7
Input from
Channels
Available Freq.
(KHz)
48
32..96
32..96
48
96
44.1 (VRA)
88.2 (VRA)
Bypass
Notes
I2S (Master)
I2S (Slave)
S/PDIF
AC’97
AC’97
AC’97
AC’97
*In this configuration the BYPASS is always active, regardless of the state (status) of SRC_Bypass bit in reg. 5Ah
7.0
PLL
To generate the required internal 49.152 MHz clock a low-jitter PLL has been included in the device. It
can be configured to work with a multiplication factor of either x8 or x2, in order to fit an external
frequency reference of 6.144 MHz or 24.576 MHz respectively. To select the multiplication factor the
PLL_Factor
bit is used. Using
PLL_Bypass
bit the PLL section can be bypassed, allowing direct
connection of the internal clock to the XTI pin. When this option is selected the PLL is automatically
powered-down and an external frequency of 49.152 MHz needs to be provided to the device. .
8.0
POWER DOWN MANAGEMENT
The power down capability and its logic behavior is shown in
Figure 3 – Powerdown management
. There
are three powerdown requests that are external to the device that will cause a power down condition:
External PWDN pin – this signal will turn-off the device, which will enter the power down mode (all
the device clocks are stopped). The device will exit this state as soon as the PWDN pin is de-
asserted.
4
4
2
6
3
4
3
Yes
No
No
Yes*
No
No
No
Bypass is user selectable
Left, Right, SL, SR, Center, LFE
Left, Right, Center
Left, Right, SL, SR
Left, Right, Center
10
Details and Specifications are subject to change without notice
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