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參數資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數： | 7/27頁 |
| 文件大小： | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
LRCKI
BICKI
SDI
T6
T5
T3
T2
T4
T1
T0
Figure 1: Input switching characteristics
4.0 I
2
S OUTPUT INTERFACE CONFIGURATION
To configure the I
2
S output interface the
Configuration Register B (CRB)
is used. Using the three
I2SO_Align_x bits one of the seven configuration modes can be selected. Table 3 describes each of
them.
Table 3
Mode
# of Slots
W. Length
Alignment
0
32
24
Left
1
32
24
Left
2
32
16
Right
3
32
24
Right
4
24
24
Left
5
Not Valid
Not Valid
Not Valid
6
24
16
Right
7
24
24
Right
By default the standard I
2
S output interface master is provided (mode 1 in bits D8, D9 and D10 of register
CRB, I2SO_BICK_Pol = 1 and I2SO_LRCK_Pol = 0 in the same register).
4.1 I
2
S Input switching characteristics (10pF load, Fsm = 48kHz) Refer to Figure 2
BICKO Frequency (master mode)
BICKO Frequency (slave mode)
BICKO pulse width low (T0) (slave mode)
BICKO pulse width high (T0) (slave mode)
BICKO active to LRCKO edge delay (T2)
BICKO active to LRCKO edge delay (T3)
SDO valid to BICKO active setup (T4)
BICKO active to SDO hold time (T5)
BICKO falling to LRCKO edge (T6) (master mode)
BICKO falling to LRCKO edge (T6) (master mode)
BICKO falling to SDO edge (T7) (master mode)
BICKO falling to SDO edge (T7) (master mode)
BICKO falling to SDO edge (T7) (slave mode)
BICKO falling to SDO edge (T7) (slave mode)
Delay Slot
No
Yes
No
No
No
Not Valid
No
No
Notes
MSb first only
Slave only
Reserved, do not use
MSb first only. Slave only
Slave only
64*Fsm
64*Fsm
40ns min.
40ns min.
20ns min.
20ns min.
20ns min.
20ns min.
2ns min.
8ns max.
2ns min.
8ns max.
6ns min.
17ns max.
7
Details and Specifications are subject to change without notice
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