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參數資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數： | 16/27頁 |
| 文件大小： | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
Filter coefficients:
CHx0 = b2
CHx1 = (b0)-1
CHx2 = a2
CHx3 = (a1)/2
CHx4 = (b1)/2
Where the CH stands for LR, SUR or SBW and x stands for the filter number (0 thru 3). The filter
equation is Y
n
= X
n
+((b0)-1)* X
n
+ 2 *((b1)/2) *X
n – 1
+ b2 *X
n – 2
– 2 * ((a1)/2) *Y
n – 1
– a2 *Y
n – 2
=
= b0 *X
n
+ b1 *X
n – 1
+ b2 *X
n – 2
– a1 *Y
n – 1
– a2 *Y
n – 2
The coefficient registers are 20 bits wide and should be in the range (-1 to 1) (80000h to 7ffffh).
Scaling factor registers:
For the filters Xn = - (-scale_in) *CHn, where CHn is the value before scaling and Xn is the input to
the filter.
For the SBW redirection SBWn = S (-scale_CH) *CHn
The scaling factor registers are 20 bits wide and should be in the range (-1 to 0) (80000h to
000000h).
SBW redirection: - 1 for maximum redirection and 0 for no redirection.
Filter scaling: -1 for maximum input and 0 for no input to filter.
11.0
I
2
C BUS SPECIFICATION
The DDX-4100 supports the I
2
C protocol. This protocol defines any device that sends data on to the bus
as a transmitter and any device that reads the data as a receiver. The device that controls the data
transfer is known as the master and the other as the slave. The master always starts the transfer and
provides the serial clock for synchronization. The DDX-4100 is always a slave device in all of its
communications.
16-bit registers are addressed as two 8-bit registers. The high byte has an even address, while the low
byte has an odd address. For example, reading from register 02 (16-bit) means read register 02 (High
Byte) and 03 (Low Byte) for I
2
C.
11.1
COMMUNICATION PROTOCOL
11.1.1 Data Transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock
is high is used to identify a START or STOP condition.
11.1.2 Start Condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is
stable in the high state. A START condition must precede any command for data transfer.
11.1.3 Stop Condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A STOP condition terminates communication between DDX-4100 and the bus master.
16
Details and Specifications are subject to change without notice
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