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| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數： | 5/27頁 |
| 文件大小： | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
2.0
The AC’97 interface is compliant with ‘Audio Codec ’97 – Revision 2.1’ specification in terms of the
protocol used. All of the registers described in this specification, including Standard, Vendor Reserved
and Extended Audio (AC’97 2.0) registers, are available in the device, however, only relevant registers
(which are described in paragraph 12, Register Summary) are implemented.
2.1
Reading AC’97 Registers
The AC’97 register bank is implemented as a contiguous RAM space, from a DSP point of view, as the
result of a read operation the content of the RAM itself will be returned. This should be followed as the
general rule, but in some cases an alternate approach is required. The following is a list of the registers
and bits where an alternate approach is required;
CodecID_0, CodecID_1:
These two bits are bits D14 and D15 of registers 28h (Extended Audio ID) and 3Ch (Extended
Modem ID). When a read operation of these registers is performed the returned value is dependent
on the status of the SA pin: CodecID_0 reports the status of SA pin, CodecID_1 always reports 0.
Other bits of these registers return the related RAM register contents. Also note that the status of the
SA pin is not readable by the DSP.
PR4
Bit D12 of register 26h (Power down, ctrl/start) is used to set the AC’97 D_CLK and SDATA_IN signal
to a low state. In response to a warm reset the status of this bit is set back to its default 0 value. In
response to a read request the actual value of this signal is returned, not the RAM content. Due to
this, the RAM register content can be inconsistent.
Regs. 2Ch, 2Eh and 30h (Audio Sample Rate Control):
These three registers are used to setup the sample rate when the Variable Rate Mode is enabled. In
response to a read request on one of these registers, the actual value returned can be either BB80h
or AC44h, depending on the status of an internal hardware signal. The status of this signal is updated
every time a write operation into one of these registers is performed.
Using the
AC97_FC_MODE
configuration bit the interface can be configured in Fully Compliant mode
(default). In this mode the value returned as a response to a read operation will be properly masked in
order to set ‘reserved’ bits to 0, per the specification. This operation is performed on all registers
including the Standard or Extended Audio address space. If the Full-Compliant mode is not selected the
full 16 bits of data from the corresponding RAM register will be returned with no further manipulation.
If an odd-addressed register reading operation is performed the following scheme is adopted:
Slot 0:
report valid bit set to 1 for both slot 1 and slot 2
Slot 1 (address):
report the odd address
Slot 2 (data):
report all 0s
2.2 Writing AC’97 Registers
When a write operation into one of the available AC’97 registers is performed the entire 16 bit data word
is written into the addressed RAM register (also
reserved
bits are passed through). Some bits of some
registers may have corresponding
hardware registers (Flip-Flops),
used to control the internal status of
the device. In this case the value of the FF is also updated every time a write to the related RAM register
is performed. The status of the FF’s are reset to their default values after either a hardware or software
reset (writing to reg. 00h) request has been issued; in which case the DSP will also have to reload the
RAM register contents.
Some registers have a different behavior from the one depicted above and are summarized below.
AC’97 REGISTER BANK OVERVIEW
5
Details and Specifications are subject to change without notice
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