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參數資料
| 型號： | MC2GH256NMCA-2SA00 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | SAMSUNG MultiMediaCard |
| 中文描述： | 三星多媒體 |
| 文件頁數： | 54/102頁 |
| 文件大小： | 1384K |
| 代理商： | MC2GH256NMCA-2SA00 |
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MultiMediaCard
TM
54
Sep.22.2005
Revision 0.3
6.3 Clock Control
The MultiMediaCard bus clock signal can be used by the host to put the card into energy saving mode, or to control the
data flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to lower the clock frequency or shut it
down.
There are a few restrictions the host must follow:
The bus frequency can be changed at any time (under the restrictions of maximum data transfer frequency, defined by
the card, and the identification frequency defined by the specification document).
It is an obvious requirement that the clock must be running for the card to output data or response tokens. After the
last MultiMediaCard bus transaction, the host is required, to provide
8 (eight)
clock cycles for the card to complete the
operation before shutting down the clock. Following is a list of the various bus transactions:
A command with no response. 8 clocks after the host command end bit.
A command with response. 8 clocks after the card response end bit.
A read data transaction. 8 clocks after the end bit of the last data block.
A write data transaction. 8 clocks after the CRC status token.
The host is allowed to shut down the clock of a “busy” card. The card will complete the programming operation
regardless of the host clock. However, the host must provide a clock edge for the card to turn off its busy signal.
Without a clock edge the card (unless previously disconnected by a deselect command -CMD7) will force the DAT0
line down, forever.
6.4 Cyclic Redundancy Codes (CRC)
The CRC is intended for protecting MultiMediaCard commands, responses and data transfer against transmission errors
on the MultiMediaCard bus. One CRC is generated for every command and checked for every response on the CMD line.
For data blocks one CRC per transferred block, per data line, is generated. The CRC is generated and checked as
described in the following.
CRC7
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and CID registers. The
CRC7 is a 7-bit value and is computed as follows:
x
7
x
3
+
+
=
x
n
second bit
(
)
×
+
×
=
x
7
(
)
G x
[
=
Generator polynomial
All CRC registers are initialized to zero. The first bit is the most left bit of the corresponding bit string (of the command,
response, CID or CSD). The degree
n
of the polynomial is the number of CRC protected bits decreased by one. The num-
ber of bits to be protected is 40 for commands and responses (n = 39), and 120 for the CSD and CID (n = 119).
Figure 6-3 : CRC7 Generator/Checker
G x
1
x
n
M x
first bit
(
)
1
–
…
last bit
(
)
x
0
×
+
+
CRC
6
…
0
[
]
Remainder
M x
]
data in
data out
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC2GH512DMCA-2SA00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:SAMSUNG MultiMediaCard |
| MC2GH512NMCA-2SA00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:SAMSUNG MultiMediaCard |
| MC2GU01GNMCA-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC2GU512NMCA-0QC00 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MultiMediaCard Specification |
| MC2M | 制造商:G & J HALL 功能描述:STEP DRILL 10-20MM 1MM STEP 制造商:G & J HALL 功能描述:STEP DRILL, 10-20MM, 1MM STEP 制造商:G & J HALL 功能描述:STEP DRILL, 10-20MM, 1MM STEP; Drill Bit Size Metric:10mm; Overall Length:77.5mm; SVHC:No SVHC (19-Dec-2012); Drill Bit Type:Step; Material:Steel; Material Thickness Max:4mm; Range:10mm - 20mm; Range:10mm - 20mm; Shank Dia:9mm; ;RoHS Compliant: NA |
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