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| 型號(hào)： | MC68HC11E0 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-channel, 8-bit analog-to-digital (A/D) converter |
| 中文描述： | 8通道，8位模擬至數(shù)字（A / D）轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 90/268頁(yè) |
| 文件大?。?/td> | 2221K |
| 代理商： | MC68HC11E0 |
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Resets and Interrupts
Data Sheet
M68HC11E Family — Rev. 5
90
Resets and Interrupts
MOTOROLA
5.2.2 External Reset (RESET)
The CPU distinguishes between internal and external reset conditions by sensing
whether the reset pin rises to a logic 1 in less than two E-clock cycles after an
internal device releases reset. When a reset condition is sensed, the RESET pin is
driven low by an internal device for four E-clock cycles, then released. Two E-clock
cycles later it is sampled. If the pin is still held low, the CPU assumes that an
external reset has occurred. If the pin is high, it indicates that the reset was initiated
internally by either the COP system or the clock monitor.
CAUTION:
Do not connect an external resistor capacitor (RC) power-up delay circuit to the
reset pin of M68HC11 devices because the circuit charge time constant can cause
the device to misinterpret the type of reset that occurred.
5.2.3 Computer Operating Properly (COP) Reset
The MCU includes a COP system to help protect against software failures. When
the COP is enabled, the software is responsible for keeping a free-running
watchdog timer from timing out. When the software is no longer being executed in
the intended sequence, a system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP
system is enabled or disabled. To change the enable status of the COP system,
change the contents of the CONFIG register and then perform a system reset. In
the special test and bootstrap operating modes, the COP system is initially
inhibited by the disable resets (DISR) control bit in the TEST1 register. The DISR
bit can subsequently be written to 0 to enable COP resets.
The COP timer rate control bits CR[1:0] in the OPTION register determine the COP
timeout period. The system E clock is divided by 2
15
and then further scaled by a
factor shown in
Table 5-1
. After reset, these bits are 0, which selects the fastest
timeout period. In normal operating modes, these bits can be written only once
within 64 bus cycles after reset.
Table 5-1. COP Timer Rate Select
CR[1:0]
Divide
E/2
15
By
XTAL = 4.0 MHz
Timeout
– 0 ms, + 32.8 ms
XTAL = 8.0 MHz
Timeout
– 0 ms, + 16.4 ms
XTAL = 12.0 MHz
Timeout
– 0 ms, + 10.9 ms
XTAL = 16.0 MHz
Timeout
– 0 ms, + 8.2 ms
0 0
1
32.768 ms
16.384 ms
10.923 ms
8.19 ms
0 1
4
131.072 ms
65.536 ms
43.691 ms
32.8 ms
1 0
16
524.28 ms
262.14 ms
174.76 ms
131 ms
1 1
64
2.098 s
1.049 s
699.05 ms
524 ms
E =
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| MC68HC11E0CB2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-channel, 8-bit analog-to-digital (A/D) converter |
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