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參數資料
| 型號： | MC68HC901FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 17/73頁 |
| 文件大?。?/td> | 274K |
| 代理商： | MC68HC901FN |
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Signal Description
2-4
MC68HC901 USER’S MANUAL
MOTOROLA
2.9 TIMER CONTROL
These lines provide internal timing and auxiliary timer control inputs required for certain
operating modes. Additionally, the timer outputs are included in this group.
2.9.1 Timer Inputs (TAI and TBI)
These input lines are control signals for timers A and B in the pulse width measurement
mode and the event count mode. These signals generate interrupts at the same priority level
as the general purpose I/O interrupt lines I4 and I3, respectively, when in the pulse width
measurement mode. While I4 and I3 do not have interrupt capability when timers A and B
are operated in this mode, they may still be used for I/O. Refer to
Measurement Mode Operation
and
Section 6.1.3 Event Count Mode Operation
further information.
Section 6.1.2 Pulse Width
for
2.9.2 Timer Outputs (TAO, TBO, TCO, and TDO)
Each timer has an associated output which toggles when its main counter counts through
01 (hexadecimal) regardless of which operational mode is selected. When in the delay
mode, the timer output will be a square wave with a period equal to two timer cycles. This
output may be used to supply the universal synchronous/asynchronous receiver-transmitter
(USART) baud rate clocks.
2.9.3 Timer Clock (XTAL1 and XTAL2)
These pins provide the timing signal for the four timers. A crystal can be connected between
the timer clock pins, XTAL1 and XTAL2, or XTAL1 can be driven with a CMOS-level clock
while XTAL2 is not connected. The following crystal parameters are suggested:
1. Parallel resonance, fundamental mode AT-cut, HC6 or HC33 holder
2. Frequency tolerance measured with 18 picofarads load (0.1% accuracy) – drive level
10 microwatts
3. Shunt capacitance equals 7 picofarads
4. Series resistance:
2.0 < f < 2.7 MHz; Rs
≤
300 ohms
2.8 < f < 4.0 MHz; Rs
≤
150 ohms
2.10 SERIAL I/O CONTROL
The full duplex serial channel is implemented by a serial input line. The independent receive
and transmit sections may be clocked by separate timing signals on the receive clock input
and the transmitter clock input.
2.10.1 Serial Input (SI)
This input line is the USART receiver data input. This input is not used in the USART
loopback mode. Refer to
Section 7.3.2 Transmitter Status Register
information.
for additional
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