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| 型號(hào)： | MC68HC901FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 37/73頁(yè) |
| 文件大小： | 274K |
| 代理商： | MC68HC901FN |
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General Purpose Input/Output Port
5-2
MC68HC901 USER’S MANUAL
MOTOROLA
the active edge register will cause the associated input to generate an interrupt on the one-
to-zero transition. Writing a one to the edge bit will produce an interrupt on the zero-to-one
transition of the corresponding line. When the processor sets a bit, interrupts will be
generated on the rising edge of the associated input signal. When the processor clears a bit,
interrupts will be generated on the falling edge of the associated input signal.
GPIP7-GPIP0 – General Purpose I/O Port
0 = Interrupts will be generated on the falling edge of the associated input signal.
1 = Interrupts will be generated on the rising edge of the associated input signal.
NOTE
The inputs to the exclusive-OR of the transition detector are the
edge bit and the input buffer. As a result, writing the AER may
cause an interrupt-producing transition, depending upon the
state of the input. So, the AER should be configured before
enabling interrupts via the interrupt enable registers (IERA and
IERB). Also, changing the edge bit while interrupts are enabled
may cause an interrupt on the corresponding channel.
5.1.3 Data Direction Register (DDR)
The data direction register (DDR) allows the programmer to define I0 through I7 as inputs
or outputs by writing the corresponding bit. When a bit of the data direction register is written
as a zero, the corresponding interrupt I/O pin will be a high-impedance input. Writing a one
to any bit of the data direction register will cause the corresponding pin to be configured as
a push-pull output.
GPIP7-GPIP0 – General Purpose I/O Port
0 = Associated I/O line is defined to be an input.
1 = Associated I/O line is defined to be an output.
AER REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
GPIP7
GPIP6
GPIP5
GPIP4
GPIP3
GPIP2
GPIP1
GPIP0
RESET
0
0
0
0
0
0
0
0
ADDR
$03
DDR REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
GPIP7
GPIP6
GPIP5
GPIP4
GPIP3
GPIP2
GPIP1
GPIP0
RESET
0
0
0
0
0
0
0
0
ADDR
$05
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