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參數資料
| 型號： | MC68HC901P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數： | 24/73頁 |
| 文件大小： | 274K |
| 代理商： | MC68HC901P |
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MOTOROLA
MC68HC901 USER’S MANUAL
4-1
SECTION 4
INTERRUPT STRUCTURE
In an M68000 system, the MFP will be assigned to one of the seven possible interrupt levels.
All interrupt service requests from the MFP 16 interrupt channels will be presented at this
level. As an interrupt controller, the MFP will internally prioritize its 16 interrupt sources.
Additional interrupt sources may be placed at the same interrupt level by daisy-chaining
multiple MFPs. The MFPs will be prioritized by their position in the chain.
4.1 INTERRUPT PROCESSING
Each MFP provides individual interrupt capability for its various functions. When an interrupt
is received on one of the external interrupt channels or from one of the eight internal
sources, the MFP will request interrupt service. The 16 interrupt channels are assigned a
fixed priority so that multiple pending interrupts are serviced according to their relative
importance. Since the MFP can internally generate 16 vector numbers, the unique vector
number which corresponds to the highest priority channel that has a pending interrupt is
presented to the processor during an interrupt acknowledge cycle. This unique vector
number allows the processor to immediately begin execution of the interrupt handler for the
interrupting source, decreasing interrupt latency.
4.1.1 Interrupt Channel Prioritization
The 16 interrupt channels are prioritized from highest to lowest, with General Purpose
Interrupt 7 (I7) being the highest and I0 the lowest. The priority of the interrupt is determined
by the least-significant four bits in the interrupt vector number which are internally generated
by the MFP. Pending interrupts are presented to the processor in order of priority unless
they have been masked. By selectively masking interrupts, the channels are in effect
re-prioritized.
4.1.2 Interrupt Vector Number
During an interrupt acknowledge cycle, a unique 8-bit interrupt vector number is presented
to the system which corresponds to the specific interrupt source that is requesting service.
V7-V4 — Vector
The four most significant bits are copied from the vector register.
BIT
7
6
5
4
3
2
1
0
FIELD
V7
V6
V5
V4
IV3
IV2
IV1
IV0
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