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參數資料
| 型號： | MC68HC901P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數： | 34/73頁 |
| 文件大小： | 274K |
| 代理商： | MC68HC901P |
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Interrupt Structure
4-11
MC68HC901 USER’S MANUAL
MOTOROLA
GPIP5-GPIP4 — General Purpose Interrupt Servicing
1 = In-service.
0 = No service in progress.
Timer C — Timer C Interrupt Servicing
1 = In-service.
0 = No service in progress.
Timer D — Timer D Interrupt Servicing
1 = In-service.
0 = No service in progress.
GPIP3-GPIP0 — General Purpose Interrupt Servicing
1 = In-service.
0 = No service in progress.
4.4 NESTING MFP INTERRUPTS
In an M68000 vectored interrupt system, the MFP is assigned to one of seven possible
interrupt levels. When an interrupt is received from the MFP, an interrupt acknowledge for
that level is initiated. Once an interrupt is recognized at a particular level, interrupts at the
same level or below are masked by the processor. As long as the processor's interrupt mask
is unchanged, the M68000 interrupt structure will prohibit nesting the interrupts at the same
interrupt level. However, additional interrupt requests from the MFP can be recognized
before a previous channel's interrupt service routine is finished by lowering the processor's
interrupt mask to the next lower interrupt level within the interrupt handler.
When nesting MFP interrupts, it may be desirable to permit interrupts on any MFP channel
regardless of its priority, to pre-empt or delay interrupt processing of an earlier channel's
interrupt service request. Or, it may be desirable to only allow subsequent higher priority
channel interrupt requests to supercede previously recognized lower priority interrupt
requests. The MFP interrupt structure provides the flexibility by offering two end-of-interrupt
options for vectored interrupt schemes. The end-of-interrupt modes are not active in a polled
interrupt scheme.
4.4.1 Selecting the End-Of-Interrupt Mode
In a vectored interrupt scheme, the MFP may be programmed to operate in either the
automatic end-of-interrupt mode or the software end-of-interrupt mode. The mode is
selected by writing the S bit of the vector register. When the S bit is programmed to a one,
ISRB REGISTER
BIT
7
6
5
4
3
2
1
0
FIELD
GPIP5
GPIP4
TIMER C
TIMER D
GPIP3
GPIP2
GPIP1
GPIP0
RESET
0
0
0
0
0
0
0
0
ADDR
$11
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