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| 型號(hào)： | MC68HC901P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Multi-Function Peripheral |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 44/73頁 |
| 文件大小： | 274K |
| 代理商： | MC68HC901P |
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MOTOROLA
MC68HC901 USER’S MANUAL
7-1
SECTION 7
UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS
RECEIVER-TRANSMITTER
The universal synchronous asynchronous receiver-transmitter (USART) is a single, full-
duplex serial channel with a double-buffered receiver and transmitter. There are separate
receive and transmit clocks and, also, separate receive and transmit status and data bytes.
The receive and transmit sections are also assigned separate interrupt channels. Each
section has two interrupt channels:
one for normal conditions
another for error conditions
All interrupt channels are edge-triggered. Generally, it is the output of a flag bit or bits which
is coupled to the interrupt channel. Thus, if an interrupt-producing event occurs while the
associated interrupt channel is disabled, no interrupt would be produced, even if the channel
was subsequently enabled because a transition did not occur while the channel was
enabled. That particular event would have to occur again, generating another edge, before
an interrupt would be generated. The interrupt channels may be disabled and instead, a
DMA device can be used to transfer the data via the control signals receiver ready (RR) and
transmitter ready (TR). Refer to
Section 7.4 DMA Operation
for more information.
7.1 CHARACTER PROTOCOLS
The MFP USART supports asynchronous and, with the help of a polynomial generator
checker, byte synchronous character formats. These formats are selected independently of
the divide-by-one and divide-by-16 clock modes. It is possible to clock data synchronously
into the MFP but still use start and stop bits. After a start bit is detected, data will be shifted
in and a stop bit will be checked to determine proper framing. In this mode, all normal
asynchronous format features apply.
When the divide-by-one clock mode is selected, synchronization must be accomplished
externally. The receiver will sample serial data on the rising edge of the receiver clock. In
the divide-by-16 clock mode, the data is sampled at mid-bit time to increase transient noise
rejection.
Also, when the divide-by-16 clock mode is selected, the USART re-synchronization logic is
enabled. This logic increases the channels clock skew tolerance. Refer to
Asynchronous Format
for more information on the re-synchronization logic.
Section 7.1.1
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