
MOTOROLA
5-4
SINGLE-CHIP INTEGRATION MODULE 2
MC68HC16R1/916R1
USER’S MANUAL
5.2.4 Show Internal Cycles
A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in SCIMCR determines what the external bus interface does during internal transfer
operations.
Table 5-1
shows whether data is driven externally, and whether external
bus arbitration can occur. Refer to
5.6.6.1 Show Cycles
for more information.
5.2.5 Register Access
MC68HC16R1/916R1 MCUs always operates at the supervisor level. The state of the
SUPV bit has no meaning.
5.2.6 Freeze Operation
The FREEZE signal halts MCU operations during debugging. FREEZE is asserted
internally by the CPU16 if a breakpoint occurs while background mode is enabled.
When FREEZE is asserted, only the bus monitor, software watchdog, and periodic in-
terrupt timer are affected. The halt monitor and spurious interrupt monitor continue to
operate normally. Setting the freeze bus monitor (FRZBM) bit in SCIMCR disables the
bus monitor when FREEZE is asserted. Setting the freeze software watchdog
(FRZSW) bit disables the software watchdog and the periodic interrupt timer when
FREEZE is asserted.
5.3 System Clock
The system clock in the SCIM2 provides timing signals for the IMB modules and for an
external peripheral bus. Because the MCU is a fully static design, register and memory
contents are not affected when the clock rate changes. System hardware and software
support changes in clock rate during operation.
The system clock signal can be generated from one of three sources. An internal
phase-locked loop (PLL) can synthesize the clock from a fast reference, a slow
reference, or the clock signal can be directly input from an external frequency source.
NOTE
Whether the PLL can use a fast or slow reference is determined by
the device. A particular device cannot use both a fast and slow
reference.
Table 5-1 Show Cycle Enable Bits
SHEN[1:0]
00
01
10
Action
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
11