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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 100/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
100
MC68HC912B32
MC68HC912B32TS/D
IE — Interrupt Enable
Determines whether the BDLC will generate CPU interrupt requests in the run mode. It does not affect
CPU interrupt requests when exiting the BDLC stop or BDLC wait modes.
0 = Disable interrupt requests from BDLC
1 = Enable interrupt requests from BDLC
WCM — Wait Clock Mode
Determines the operation of the BDLC during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
1 = Stop BDLC internal clocks during CPU wait mode
Controls transmitter operations of the BDLC.
ALOOP — Analog Loopback Status
Sets the BDLC state machine to a known state after the off-chip analog transceiver has been put in loop
back mode.
0 = Off-chip analog transceiver has been taken out of analog loopback mode
1 = Off-chip analog transceiver has been put into analog loopback mode
DLOOP — Digital Loopback Mode
Determines the RxPD source and can isolate bus fault conditions. If a fault condition is detected on the
bus, RxPD can be disconnected from the analog transceiver’s receive output and connected to TxPD
to determine if the fault is in the digital block or elsewhere on the J1850 bus.
0 = RxPD is connected to the analog transceiver’s receive output. The BDLC is taken out of digital
loopback mode and can now drive and receive from the J1850 bus normally if ALOOP is not set.
1 = RxPD is connected to TxPD. The BDLC is now in digital loopback mode of operation. The an-
alog transceiver’s transmit input is still driven by TxPD.
Table 32 BDLC Rate Selection for Binary Frequencies
(f
BDLC
= 1.048576 MHz)
MCU Clock Frequency (
f
TCLKS
)
1.048576 MHz
2.09715 MHz
4.19430 MHz
8.38861 MHz
R1
R0
Division
0
0
1
1
0
1
0
1
1
2
4
8
Table 33 BDLC Rate Selection for Integer Frequencies
(f
BDLC
= 1.000000 MHz)
MCU Clock Frequency (
f
TCLKS
)
1.00000 MHz
2.00000 MHz
4.00000 MHz
8.00000 MHz
R1
R0
Division
0
0
1
1
0
1
0
1
1
2
4
8
BCR2 —
BDLC Control Register 2
$00FA
Bit 7
6
5
4
3
2
1
Bit 0
ALOOP
DLOOP
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
RESET:
1
1
0
0
0
0
0
0
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