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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 40/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
40
MC68HC912B32
MC68HC912B32TS/D
ENPE — Enable Programming/Erase
0 = Disables program/erase voltage to Flash EEPROM
1 = Applies program/erase voltage to Flash EEPROM
ENPE can be asserted only after LAT has been asserted and a write to the data and address latches
has occurred. If an attempt is made to assert ENPE when LAT is negated, or if the latches have not
been written to after LAT was asserted, ENPE will remain negated after the write cycle is complete.
The LAT, ERAS and BOOTP bits cannot be changed when ENPE is asserted. A write to FEECTL may
only affect the state of ENPE. Attempts to read a Flash EEPROM array location in the Flash EEPROM
module while ENPE is asserted will not return the data addressed. See
Table 14
for more information.
Flash EEPROM module control registers may be read or written while ENPE is asserted. If ENPE is
asserted and LAT is negated on the same write access, no programming or erasure will be performed.
7.5 Operation
The Flash EEPROM can contain program and data. On reset, it can operate as a bootstrap memory to
provide the CPU with internal initialization information during the reset sequence.
7.5.1 Bootstrap Operation Single-Chip Mode
After reset, the CPU controlling the system will begin booting up by fetching the first program address
from address $FFFE.
7.5.2 Normal Operation
The Flash EEPROM allows a byte or aligned word read/write in one bus cycle. Misaligned word read/
write require an additional bus cycle. The Flash EEPROM array responds to read operations only. Write
operations are ignored.
7.5.3 Program/Erase Operation
An unprogrammed Flash EEPROM bit has a logic state of one. A bit must be programmed to change
its state from one to zero. Erasing a bit returns it to a logic one. The Flash EEPROM has a minimum
program/erase life of 100 cycles. Programming or erasing the Flash EEPROM is accomplished by a se-
ries of control register writes and a write to a set of programming latches.
Programming is restricted to a single byte or aligned word at a time as determined by internal signal
SZ8 and ADDR[0]. The Flash EEPROM must first be completely erased prior to programming final data
values. It is possible to program a location in the Flash EEPROM without erasing the entire array if the
new value does not require the changing of bit values from zero to one.
Read/Write Accesses During Program/Erase
— During program or erase operations, read and write
accesses may be different from those during normal operation and are affected by the state of the con-
trol bits in the Flash EEPROM control register (FEECTL). The next write to any valid address to the ar-
ray after LAT is set will cause the address and data to be latched into the programming latches. Once
the address and data are latched, write accesses to the array will be ignored while LAT is set. Writes to
the control registers will occur normally.
Program/Erase Verification
— When programming or erasing the Flash EEPROM array, a special
verification method is required to ensure that the program/erase process is reliable, and also to provide
Table 14 Effects of ENPE, LAT and ERAS on Array Reads
ENPE
0
0
0
1
LAT
0
1
1
–
ERAS
–
0
1
–
Result of Read
Normal read of location addressed
Read of location being programmed
Normal read of location addressed
Read cycle is ignored
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