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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 34/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
34
MC68HC912B32
MC68HC912B32TS/D
This register is associated with external bus control signals and interrupt inputs including data bus en-
able (DBE), mode select (MODB/IPIPE1, MODA/IPIPE0), E clock, data size (LSTRB/TAGLO), read/
write (R/W), IRQ, and XIRQ. When the associated pin is not used for one of these specific functions,
the pin can be used as general-purpose I/O. The port E assignment register (PEAR) selects the function
of each pin. DDRE determines the primary direction of each port E pin when configured to be general-
purpose I/O.
Some of these pins have software selectable pull-ups (DBE, LSTRB, R/W, and XIRQ). A single control
bit enables the pull-ups for all these pins which are configured as inputs. IRQ always has a pull-up.
This register is not in the map in peripheral mode or expanded modes when the EME bit is set.
Read and write anytime.
This register determines the primary direction for each port E pin configured as general-purpose I/O.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
PE[1:0] are associated with XIRQ and IRQ and cannot be configured as outputs. These pins can be
read regardless of whether the alternate interrupt functions are enabled.
This register is not in the map in peripheral mode and expanded modes while the EME control bit is set.
Read and write anytime.
The PEAR register is used to choose between the general-purpose I/O functions and the alternate bus
control functions of port E. When an alternate control function is selected, the associated DDRE bits are
overridden.
The reset condition of this register depends on the mode of operation because bus-control signals are
needed immediately after reset in some modes.
In normal single-chip mode, no external bus control signals are needed so all of port E is configured for
general-purpose I/O.
PORTE —
Port E Register
$0008
Bit 7
6
5
4
3
2
1
Bit 0
Single Chip
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
–
–
–
–
–
–
–
–
Alt. Pin
Function
DBE
MODB or
IPIPE1
MODA or
IPIPE0
ECLK
LSTRB or
TAGLO
R/W
IRQ
XIRQ
DDRE —
Port E Data Direction Register
$0009
Bit 7
6
5
4
3
2
1
Bit 0
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
0
0
RESET:
0
0
0
0
0
0
–
–
PEAR —
Port E Assignment Register
$000A
Bit 7
6
5
4
3
2
1
Bit 0
NDBE
0
PIPOE
NECLK
LSTRE
RDWE
0
0
RESET:
0
–
0
0
0
0
–
–
Normal
Expanded
RESET:
0
–
1
0
1
1
–
–
Special
Expanded
RESET:
1
–
0
1
0
0
–
–
Peripheral
RESET:
1
–
0
1
0
0
–
–
Normal
Single Chip
RESET:
0
–
1
0
1
1
–
–
Special
Single Chip
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