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參數(shù)資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 111/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
111
The ATD control register 5 is used to select the conversion modes, the conversion channel(s), and ini-
tiate conversions.
Read or write anytime. Writes to the ATD control registers initiate a new conversion sequence. If a con-
version sequence is in progress when a write occurs, that sequence is aborted and the SCF and CCF
bits are reset.
S8CM — Select 8 Channel Mode
0 = Conversion sequence consists of four conversions
1 = Conversion sequence consists of eight conversions
SCAN — Enable Continuous Channel Scan
0 = Single conversion sequence
1 = Continuous conversion sequences (scan mode)
When a conversion sequence is initiated by a write to the ATDCTL register, the user has a choice of
performing a sequence of four (or eight, depending on the S8CM bit) conversions or continuously per-
forming four (or eight) conversion sequences.
MULT — Enable Multichannel Conversion
0 = ATD sequencer runs all four or eight conversions on a
single
input channel selected via the
CD, CC, CB, and CA bits.
1 = ATD sequencer runs each of the four or eight conversions on
sequential
channels in a specific
group. Refer to
Table 41
.
CD, CC, CB, and CA — Channel Select for Conversion
NOTES:
1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become
maximum conversion rate that can be used on this ATD module.
2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value will become
minimum conversion rate that this ATD can perform.
Table 40 Clock Prescaler Values
Prescale Value
Total Divisor
÷
2
÷
4
÷
6
÷
8
÷
10
÷
12
÷
14
÷
16
Max P Clock
1
Min P Clock
2
00000
4 MHz
1 MHz
00001
8 MHz
2 MHz
00010
8 MHz
3 MHz
00011
8 MHz
4 MHz
00100
8 MHz
5 MHz
00101
8 MHz
6 MHz
00110
8 MHz
7 MHz
00111
8 MHz
8 MHz
01xxx
1xxxx
Do Not Use
ATDCTL5
— ATD Control Register 5
$0065
Bit 7
6
5
4
3
2
1
Bit 0
0
S8CM
SCAN
MULT
CD
CC
CB
CA
RESET:
0
0
0
0
0
0
0
0
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