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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 80/128頁 |
| 文件大?。?/td> | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
80
MC68HC912B32
MC68HC912B32TS/D
PEDGE — Pulse Accumulator Edge Control
For PAMOD = 0 (event counter mode)
0 = Falling edges on the pulse accumulator input pin (PT7/PAI) cause the count to be incremented
1 = Rising edges on the pulse accumulator input pin cause the count to be incremented
For PAMOD = 1 (gated time accumulation mode)
0 = Pulse accumulator input pin high enables E
÷
64 clock to pulse accumulator and the trailing fall-
ing edge on the pulse accumulator input pin sets the PAIF flag.
1 = Pulse accumulator input pin low enables E
÷
64 clock to pulse accumulator and the trailing rising
edge on the pulse accumulator input pin sets the PAIF flag.
If the timer is not active (TEN = 0 in TSCR), there is no
÷
64 clock since the E
÷
64 clock is generated
by the timer prescaler.
CLK1, CLK0 — Clock Select Register
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as
an input clock to the timer counter. The change from one selected clock to the other happens immedi-
ately after these bits are written.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 = Interrupt inhibited
1 = Interrupt requested if PAOVF is set
PAI — Pulse Accumulator Input Interrupt Enable
0 = Interrupt inhibited
1 = Interrupt requested if PAIF is set
Read or write anytime.
When TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in
the PAFLG register.
PAOVF — Pulse Accumulator Overflow Flag
Set when the 16-bit pulse accumulator overflows from $FFFF to $0000. This bit is cleared automatically
by a write to the PAFLG register with bit 1 set.
PAIF — Pulse Accumulator Input Edge Flag
Set when the selected edge is detected at the pulse accumulator input pin. In event mode, the event
edge triggers PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the pulse
accumulator input pin triggers PAIF. This bit is cleared automatically by a write to the PAFLG register
with bit 0 set.
Table 27 Clock Selection
CLK1
0
0
1
1
CLK0
0
1
0
1
Selected Clock
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
PAFLG
— Pulse Accumulator Flag Register
$00A1
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
PAOVF
PAIF
RESET:
0
0
0
0
0
0
0
0
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