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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 104/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
104
MC68HC912B32
MC68HC912B32TS/D
Used to pass data to be transmitted to the J1850 bus from the CPU to the BDLC. It is also used to pass
data to the CPU. Each data byte (after the first one) should be written only after a “Tx Data Register
Empty” (TDRE) interrupt has occurred, or the BSVR register has been polled indicating this condition.
Data read from this register will be the last data byte received from the J1850 bus and should be read
only after a “Rx Data Register Full” (RDRF) or a “Received IFR Byte” (RXIFR) interrupt has occurred,
or the BSVR register has been polled indicating this condition.
To stop a transmission that is already in progress simply stop loading more data into the BDR. This will
cause a transmitter underrun error and the BDLC will automatically disable the transmitter on the next
non-byte boundary.
Programs the BDLC to compensate for various delays of external transceivers. Read anytime. May be
written once in normal modes or written anytime in special mode.
ATE — Analog Transceiver Enable
0 = Select off-chip analog transceiver
1 = Select on-board analog transceiver
NOTE
This device does not contain an on-board transceiver. The ATE bit should be pro-
grammed to a logic zero for proper operation.
RXPOL — Receive Pin Polarity
This bit selects the polarity of the incoming signal on the receive pin.
0 = Select inverted polarity, where external transceiver inverts the receive signal.
1 = Select normal/true polarity; true non-inverted signal from J1850 bus, i.e., the external transceiv-
er does not invert the receive signal.
BO[3:0] — BARD Offset
These bits are used to compensate for the analog transceiver roundtrip delay. The following table
shows the expected transceiver delay with respect to BARD offset values:
BDR —
BDLC Data Register
$00FB
Bit 7
6
5
4
3
2
1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
RESET:
–
–
–
–
–
–
–
–
BARD —
BDLC Analog Roundtrip Delay Register
$00FC
Bit 7
6
5
4
3
2
1
Bit 0
ATE
RXPOL
0
0
BO3
BO2
BO1
BO0
RESET:
1
1
0
0
0
1
1
1
Table 36 Offset Bit Values and Transceiver Delay
BARD Offset Bits
(BO3, BO2, BO1, BO0)
0000
0001
0010
0011
0100
Expected Delay (
μ
s
)
9
10
11
12
13
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