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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 27/128頁 |
| 文件大?。?/td> | 748K |
| 代理商： | MC68B912B32 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
27
MODE controls the MCU operating mode and various configuration options. This register is not in the
map in peripheral mode.
SMODN, MODB, MODB — Mode Select Special, B and A
These bits show the current operating mode and reflect the status of the BKGD, MODB and MODA input
pins at the rising edge of reset.
Read anytime. SMODN may only be written if SMODN = 0 (in special modes) but the first write is ig-
nored; MODB, MODA may be written once if SMODN = 1; anytime if SMODN = 0, except that special
peripheral and reserved modes cannot be selected.
ESTR — E Clock Stretch Enable
Determines if the E Clock behaves as a simple free-running clock or as a bus control signal that is active
only for external bus cycles. ESTR is always one in expanded modes since it is required for address
demultiplexing and must follow stretched cycles.
0 = E never stretches (always free running).
1 = E stretches high during external access cycles and low during non-visible internal accesses.
Normal modes: write once; Special modes: write anytime, read anytime.
IVIS — Internal Visibility
This bit determines whether internal ADDR/DATA, R/W, and LSTRB signals can be seen on the bus
during accesses to internal locations. In special expanded narrow mode, it is possible to configure the
MCU to show internal accesses on an external 16-bit bus. The IVIS control bit must be set to one. When
the system is configured this way, visible internal accesses are shown as if the MCU was configured for
expanded wide mode but normal external accesses operate as if the bus was in narrow mode. In normal
expanded narrow mode, internal visibility is not allowed and IVIS is ignored.
0 = No visibility of internal bus operations on external bus
1 = Internal bus operations are visible on external bus
Normal modes: write once; Special modes: write anytime EXCEPT the first time. Read anytime.
EBSWAI — External Bus Module Stop in Wait Control
This bit controls access to the external bus interface when in wait mode. The module will delay before
shutting down in wait mode to allow for final bus activity to complete.
0 = External bus and registers continue functioning during wait mode.
1 = External bus is shut down during wait mode.
MODE —
Mode Register
$000B
Bit 7
6
5
4
3
2
1
Bit 0
SMODN
MODB
MODA
ESTR
IVIS
EBSWAI
0
EME
RESET:
1
0
1
1
0
0
–
0
Normal Exp
Narrow
RESET:
1
1
1
1
0
0
–
0
Normal Exp
Wide
RESET:
0
0
1
1
1
0
–
1
Special Exp
Narrow
RESET:
0
1
1
1
1
0
–
1
Special Exp
Wide
RESET:
0
1
0
1
1
0
–
1
Peripheral
RESET:
1
0
0
1
0
0
–
0
Normal
Single Chip
RESET:
0
0
0
1
1
0
–
1
Special
Single Chip
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