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參數資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數： | 16/128頁 |
| 文件大?。?/td> | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
16
MC68HC912B32
MC68HC912B32TS/D
When the PUPE bit in the PUCR register is set, PE[7,3,2,0] are pulled up. PE[7,3,2,0] are pulled up ac-
tive devices, while PE1 is always pulled up by means of an internal resistor.
Neither port E nor DDRE is in the map in peripheral mode; neither is in the internal map in expanded
modes with EME set.
Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced drive level. RDRIV
can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to
6 Bus
Control and Input/Output
.
3.4.4 Port DLC
BDLC pins can be configured as general-purpose I/O port DLC. When BDLC functions are not enabled,
the port has seven general-purpose I/O pins, PDLC[6:0]. The DLCSCR register controls port DLC func-
tion. The BDLC function, enabled with the BDLCEN bit, takes precedence over other port functions.
Register DDRDLC determines whether each port DLC pin is an input or output. Setting a bit in DDRDLC
makes the corresponding pin in port DLC an output; clearing a bit makes the corresponding pin an input.
After reset port DLC pins are configured as inputs.
When the PUPDLC bit in the DLCSCR register is set, all port DLC input pins are pulled up internally by
an active pull-up device.
Setting the RDPDLC bit in register DLCSCR causes all port DLC outputs to have reduced drive level.
Levels are at normal drive capability after reset. RDPDLC can be written anytime after reset. Refer to
14 Byte Data Link Communications Module (BDLC)
.
3.4.5 Port AD
Input to the analog-to-digital subsystem and general-purpose input. When analog-to-digital functions
are not enabled, the port has eight general-purpose input pins, PAD[7:0]. The ADPU bit in the ATDCTL2
register enables the A/D function.
Port AD pins are inputs; no data direction register is associated with this port. The port has no resistive
input loads and no reduced drive controls. Refer to
15 Analog-To-Digital Converter
.
3.4.6 Port P
The four pulse-width modulation channel outputs share general-purpose port P pins. The PWM function
is enabled with the PWEN register. Enabling PWM pins takes precedence over the general-purpose
port. When pulse-width modulation is not in use, the port pins may be used for general-purpose I/O.
Register DDRP determines pin direction of port P when used for general-purpose I/O. When DDRP bits
are set, the corresponding pin is configured for output. On reset the DDRP bits are cleared and the cor-
responding pin is configured for input.
When the PUPP bit in the PWCTL register is set, all input pins are pulled up internally by an active pull-
up device. Pull-ups are disabled after reset.
Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels.
Levels are at normal drive capability after reset. The PWCTL register can be read or written anytime
after reset. Refer to
11 Pulse-Width Modulator
.
3.4.7 Port T
This port provides eight general-purpose I/O pins when not enabled for input capture and output com-
pare in the timer and pulse accumulator subsystem. The TEN bit in the TSCR register enables the timer
function. The pulse accumulator subsystem is enabled with the PAEN bit in the PACTL register.
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