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參數(shù)資料
| 型號： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 33/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
33
Bits PA[7:0] are associated with addresses ADDR[15:8] and DATA[15:8]. When this port is not used for
external addresses and data, such as in single-chip mode, these pins can be used as general-purpose
I/O. DDRA determines the primary direction of each pin. This register is not in the on-chip map in ex-
panded and peripheral modes. Read and write anytime.
This register determines the primary direction for each port A pin when functioning as a general-purpose
I/O port. DDRA is not in the on-chip map in expanded and peripheral modes. Read and write anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0]. When this port is not used for
external addresses and data such as in single-chip mode, these pins can be used as general-purpose
I/O. DDRB determines the primary direction of each pin. This register is not in the on-chip map in ex-
panded and peripheral modes. Read and write anytime.
This register determines the primary direction for each port B pin when functioning as a general-purpose
I/O port. DDRB is not in the on-chip map in expanded and peripheral modes. Read and write anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
PORTA —
Port A Register
$0000
Bit 7
6
5
4
3
2
1
Bit 0
Single
Chip
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
–
–
–
–
–
–
–
–
Exp Wide
& Periph:
ADDR15
DATA15
ADDR14
DATA14
ADDR13
DATA13
ADDR12
DATA12
ADDR11
DATA11
ADDR10
DATA10
ADDR9
DATA9
ADDR8
DATA8
Expanded
Narrow
ADDR15
DATA15/7
ADDR14
DATA14/6
ADDR13
DATA13/5
ADDR12
DATA12/4
ADDR11
DATA11/3
ADDR10
DATA10/2
ADDR9
DATA9/1
ADDR8
DATA8/0
DDRA —
Port A Data Direction Register
$0002
Bit 7
6
5
4
3
2
1
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
RESET:
0
0
0
0
0
0
0
0
PORTB —
Port B Register
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Single Chip
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
–
–
–
–
–
–
–
–
Exp Wide
& Periph:
ADDR7
DATA7
ADDR6
DATA6
ADDR5
DATA5
ADDR4
DATA4
ADDR3
DATA3
ADDR2
DATA2
ADDR1
DATA1
ADDR0
DATA0
Expanded
Narrow
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
DDRB —
Port B Data Direction Register
$0003
Bit 7
6
5
4
3
2
1
Bit 0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
RESET:
0
0
0
0
0
0
0
0
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