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參數(shù)資料
| 型號(hào)： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁數(shù)： | 94/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32 |
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MOTOROLA
94
MC68HC912B32
MC68HC912B32TS/D
Read or write anytime.
SPIE — SPI Interrupt Enable
1 = Hardware interrupt sequence is requested each time the SPIF or MODF status flag is set
0 = SPI interrupts are inhibited
SPE — SPI System Enable
0 = SPI internal hardware is initialized and SPI system is in a low-power disabled state.
1 = PS[4:7] are dedicated to the SPI function
When MODF is set, SPE always reads zero. SP0CR1 must be written as part of a mode fault recovery
sequence.
SWOM — Port S Wired-OR Mode
Controls not only SPI output pins but also the general-purpose output pins (PS[4:7]) which are not used
by SPI.
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain outputs
MSTR — SPI Master/Slave Mode Select
0 = Slave mode
1 = Master mode
CPOL, CPHA — SPI Clock Polarity, Clock Phase
These two bits are used to specify the clock format to be used in SPI operations. When the clock polarity
bit is cleared and data is not being transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See
Figure 22
and
Figure 23
.
SSOE — Slave Select Output Enable
The SS output feature is enabled only in the master mode by asserting the SSOE and DDS7.
LSBF — SPI LSB First Enable
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
Normally data is transferred most significant bit first. This bit does not affect the position of the MSB and
LSB in the data register. Reads and writes of the data register will always have MSB in bit 7.
Read or write anytime.
SSWAI — SSI Stop in Wait Mode
0 = SSI clock operate normally
1 = Halt SSI clock generation when in wait mode
SPC0 — Serial Pin Control 0
This bit decides serial pin configurations with MSTR control bit.
SP0CR2
— SPI Control Register 2
$00D1
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
SSWAI
SPC0
RESET:
0
0
0
0
0
0
0
0
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